DRP3510A Просмотр технического описания (PDF) - Micronas

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Компоненты Описание

производитель

DRP3510A

Digital Radio Processor

Micronas 

ADVANCE INFORMATION

DRP 3510A

Pin No.

PLCC

44-pin

37

38

39

40

41

42

43

44

Connection

(if not used)

LV

LV

VDD_10k

VDD_10k

LV

LV

LV

NC

Pin Name

PI18 (CRCE)

PI19 (FSI)

PCSQ

PR

PRTWQ

PRTRQ

EODQ

Type

Short Description

(IN/OUT) O

(IN/OUT) O

IN

IN

OUT

OUT

OUT

PIO DATA [18] (CRC-error)

PIO DATA [19] (frame start impulse, low active)

PIO Chip Select

PIO Read/Write

PIO Ready to Write

PIO Ready to Read

PIO End of DMA

3.3. Pin Descriptions

3.3.1. VDD, AVDD, VSS, AVSS

VDD and AVDD should be blocked against VSS and

AVSS. For proper operation and in order to avoid EMV

problems, a capacitive blocking of VDD against VSS

over a wide frequency range is recommended.

3.3.2. I2CD

The I2CD line is used for I2C data transfers from the DRP

to a controller and vice versa.

3.3.3. I2CC

The I2C clock line is used for the I2C clock if the IC is in

the operation mode. However, on a power on reset, the

I2C line determines the operating mode of the internal

clock generator of the DRP. If the I2CC line is set to low

during power on reset, the internal DRP clock is directly

taken from the crystal input XTI and the internal crystal

oscillator is disabled. In standard ADR mode, the I2C

clock pin has to set to high level, in order to activate the

internal oscillator and the internal DCO, which is used to

synchronize the DRP clock system with the data rate of

the incoming ADR signal.

3.3.4. PORQ

Reset input (active low). The minimum length of a reset

impulse should be 100 µs. See the timing diagrams (sec-

tion 12.) for the recommended power up sequence and

further details.

Micronas

3.3.5. CLKO

If the DRPA is driven with a 24.576 MHz quartz, the

CLKO pin delivers a synchronized 18.432 MHz clock,

otherwise the the CLKO pin is muted.

3.3.6. XTI, XTO

The crystal input XTI can either be used for the crystal

application or for a direct input of a clock signal with the

correct frequency. If the XTI signal is used for direct in-

put, the input signal has to be DC-free, a minimum level

of 0.7 Vss and a maximum level of 3 Vss.The XTO signal

is the output of the internal crystal oscillator.

3.3.7. TE

The TE pin is reserved for chip testing only. For customer

applications, this pin must always be connected to VSS.

3.3.8. PI0..PI3

In standard PIO mode, these pins are static input pins

that allow the selection of different operating modes.

The PI0 pin is used to select the used crystal frequency.

The level of the PI0 pin is evaluated within 10 ms after

reset. The PI3 pin is used to select the basic operating

mode (either ADR or L2-only decoding). The PI1 and PI2

inputs are reserved for future use and have to be set to

‘0’. Because these PIx pins are generally used as input

pins, it is recommended to connect them with a fixed po-

tential. However, in DMA output mode, they operate as

output pins. Thus, their connection with VSS or VDD

should be done via 10 k resistors in order to avoid short-

circuits.

3.3.9. SO1C, SO1I, SO1D

These three serial data output lines transport the de-

coded ADR/DMX signal at a sample rate of 32 kHz. An

9

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