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DRP3510A

Digital Radio Processor

Micronas 

ADVANCE INFORMATION

DRP 3510A

Digital Radio Processor

1. Introduction

The DRP 3510A decodes digital audio data transmitted

according to the Astra Digital Radio standard1). The

DRP 3510A has a well-defined interface to the Multi-

standard Sound Processor MSP 3400C. The

DRP 3510A and the MSP 3400C (alternatively MSP

3410D2)) provide all functions that are necessary for

ADR and DMX3) decoding. The IC is manufactured in a

low-cost 0.8 µm CMOS technology and housed in a

44-pin PLCC package.

The DRP is designed as a coprocessor for the MSP,

which may already be used in a standard satellite receiv-

er. The video baseband A/D converter, the channel

selection, some preprocessing of the digital audio sub-

carrier, and the TV-sound output are shared with the

MSP. Only those parts that are additionally required for

ADR-decoding are implemented in the DRP. Thus, up-

grading of existing receiver concepts for ADR compati-

bility is comparably simple and generates a minimum of

additional costs.

The core of the digital radio processor is based on the

Micronas MASC DSP. A very important feature of the

MASC core is its two operating modes: the standard

mode that works with 20-bit fixed point numbers and the

complex mode that works with 2*10-bit numbers, con-

sisting of a10-bit fixed point real part and a 10-bit fixed

point imaginary part. This feature offers the opportunity

of using the same processor for different tasks like

QPSK channel demodulation, MPEG Layer 2 source de-

coding, and system controlling. Consequently, most

parts of the ADR decoder are implemented as firmware

and could easily be updated if required.

A special controllable viterbi module has been inte-

grated with a burst decoding rate of 2 MBit/s. The data

transport between the viterbi module and the DSP is

done in the background with an internal non-cycle steal-

ing DMA. This is exactly the same kind of transport

mechanism that is used between the processor core and

its various interfaces. The complete data-I/O handling is

pushed into the background and does not affect the

main processing.

48 kHz

SP/DIF(0)

(IEC 958)

48 kHz

SDO(0)

ADR(1)

32 kHz

SDO(1)

DRP 3510A

MASC Processor Core

parallel port

I2C

Viterbi

Decoder

18.432 MHz or

24.576 MHz

Fig. 1–1: DRP 3510A interfaces

1) ASTRA ADR/Rev. 1.3 SYS –078/02–94 TW/ab 15 December 1994

2) MSP 3410D is derived from MSP 3400C with an added NICAM decoding feature.

3) Digital Music Express (for DMX decoding, a verifier-IC and a smartcard reader is additionally required)

Micronas

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