DRP3510A Просмотр технического описания (PDF) - Micronas

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производитель

DRP3510A

Digital Radio Processor

Micronas 

DRP 3510A

ADVANCE INFORMATION

internal sample rate converter performs the 48 to 32 kHz

downsampling. For proper ADR-operation, it is manda-

tory to connect them with one I2S input of the MSP. The

MSP clock system has to be switched into ‘slave mode’.

The data word is not delayed vs. the word-strobe (SO1I)

signal.

3.3.10. SI1C, SI1D, SI1I (ADR input interface)

The ADR input interface has to be connected with the

ADR/S-Bus interface of the MSP chip. In Layer 2 mode,

the lines SI1C (for clock) and SI1D (for data) will expect

a valid Layer 2 data stream.

3.3.11. SPDIF

The SPDIF interface provides the ADR/DMX data in the

digital SPDIF format, in accordance with the consumer

standard IEC 958.

3.3.12. SO0C, SO0I, SO0D

The SO0 output interface is the standard interface for a

48 kHz additional DAC, for full sampling rate output,

which is not implemented in the MSP. The data word is

not delayed vs. the word-strobe (SO1I) signal by default.

3.3.13. SI1C*, SI1D*, SI1I* (PI14..16)

These lines are used as alternative input lines and could

be connected e.g. with the I2S output of the MSP. How-

ever, these input pins are not supported by the built-in

firmware. Downloaded program codes can use these in-

put lines for alternative functionality of the DRP. An ex-

ample for an adequate download program is an I2S to

SP/DIF converter program that can be used to map the

analog FM-sound signal from the MSP to the SP/DIF

output interface of the DRP. In the standard ADR-mode,

these lines are input pins that should be connected via

resistors to a fixed level (VSS).

3.3.14. PI12..PI19

In standard ADR mode, the PIO pin PI19 shows the

Frame Start Impulse (FSI). This impulse is synchronized

with the MPEG frame and is set to low level for at maxi-

mum 23 ms, which indicates that a new ADR ancillary

data block is available for read-out via I2C. The CRC-er-

ror pin PI18 will be set to high level for 24 ms (duration

of one MPEG Layer 2 frame) when an MPEG CRC error

has been detected. In DMA mode, the PI12..PI19 pins

will contain the 8-bit aligned undecoded MPEG data

stream.

3.3.15. EODQ, PRTWQ, PR, (PRTRQ, PCSQ)

For a description of EODQ, PRTRQ, PR, see section

6.4.2. The PRTRQ line is reserved for future use. The

PCSQ line is not used by the actual firmware and should

be connected to VDD via a resistor.

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