74HC132-Q100 Просмотр технического описания (PDF) - NXP Semiconductors.
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74HC132-Q100 Datasheet PDF : 19 Pages
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Nexperia
74HC132-Q100; 74HCT132-Q100
Quad 2-input NAND Schmitt trigger
5 Functional diagram
1 1A
2 1B
1Y 3
4 2A
5 2B
2Y 6
9 3A
10 3B
3Y 8
12 4A
13 4B
4Y 11
mna407
Figure 1. Logic symbol
1
&
3
2
4
&
6
5
9
&
8
10
12
&
11
13
mna408
Figure 2. IEC logic symbol
6 Pinning information
A
Y
B
mna409
Figure 3. Logic diagram
(one Schmitt trigger)
6.1 Pinning
74HC132-Q100
74HCT132-Q100
1A 1
1B 2
1Y 3
2A 4
2B 5
2Y 6
GND 7
14 VCC
13 4B
12 4A
11 4Y
10 3B
9 3A
8 3Y
aaa-003901
Figure 4. Pin configuration SOT108-1 (SO14) and
SOT402-1 (TSSOP14)
74HC132-Q100
terminal 1
index area
1B 2
1Y 3
2A 4
2B 5
2Y 6
GND(1)
13 4B
12 4A
11 4Y
10 3B
9 3A
aaa-028548
Transparent top view
(1) This is not a supply pin. The substrate is attached to
this pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Figure 5. Pin configuration SOT762-1 (DHVQFN14)
74HC_HCT132_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 12 June 2018
© Nexperia B.V. 2018. All rights reserved.
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