ATMEGA32(2008) Просмотр технического описания (PDF) - Atmel Corporation

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ATMEGA32
(Rev.:2008)

8-bit Microcontroller with 32K Bytes In-System Programmable Flash

Atmel Corporation 

ATmega32(L)

ALU – Arithmetic

Logic Unit

Program Flash memory space is divided in two sections, the Boot program section and the

Application Program section. Both sections have dedicated Lock bits for write and read/write

protection. The SPM instruction that writes into the Application Flash memory section must

reside in the Boot Program section.

During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the

Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack

size is only limited by the total SRAM size and the usage of the SRAM. All user programs must

initialize the SP in the reset routine (before subroutines or interrupts are executed). The Stack

Pointer SP is read/write accessible in the I/O space. The data SRAM can easily be accessed

through the five different addressing modes supported in the AVR architecture.

The memory spaces in the AVR architecture are all linear and regular memory maps.

A flexible interrupt module has its control registers in the I/O space with an additional global

interrupt enable bit in the Status Register. All interrupts have a separate interrupt vector in the

interrupt vector table. The interrupts have priority in accordance with their interrupt vector posi-

tion. The lower the interrupt vector address, the higher the priority.

The I/O memory space contains 64 addresses for CPU peripheral functions as Control Regis-

ters, SPI, and other I/O functions. The I/O Memory can be accessed directly, or as the Data

Space locations following those of the Register File, $20 - $5F.

The high-performance AVR ALU operates in direct connection with all the 32 general purpose

working registers. Within a single clock cycle, arithmetic operations between general purpose

registers or between a register and an immediate are executed. The ALU operations are divided

into three main categories – arithmetic, logical, and bit-functions. Some implementations of the

architecture also provide a powerful multiplier supporting both signed/unsigned multiplication

and fractional format. See the “Instruction Set” section for a detailed description.

9

2503N–AVR–06/08

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