CY7C1061DV33-10BVXI Просмотр технического описания (PDF) - Cypress Semiconductor

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производитель

CY7C1061DV33-10BVXI

16-Mbit (1 M × 16) Static RAM

Cypress Semiconductor 

CY7C1061DV33

Data Retention Characteristics

Over the Operating Range

Parameter

Description

Conditions

Min

VDR

VCC for data retention

–

2

ICCDR

Data retention current

VCC = 2 V, CE1 > VCC – 0.2 V, CE2 < 0.2 V,

–

VIN > VCC – 0.2 V or VIN < 0.2 V

tCDR [14]

Chip deselect to data retention –

0

time

tR[15]

Operation recovery time

–

tRC

Data Retention Waveform

VCC

CE

Figure 6. Data Retention Waveform [16]

3.0 V

tCDR

Data Retention Mode

VDR > 2 V

3.0 V

tR

Max Unit

–

V

25

mA

–

ns

–

ns

Switching Waveforms

Figure 7. Read Cycle No. 1 (Address Transition Controlled) [17, 18]

Address

Data Out

tRRCC

tAA

tOHA

Previous Data Valid

Data Valid

Notes

14. Tested initially and after any design or process changes that may affect these parameters.

15. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 50 s or stable at VCC(min.) > 50 s.

16.

For

CE

all packages

is HIGH. For

except

-BV1XI

-BV1XI, CE is the logical combination

package, CE refers to CE.

of

CE1

and

CE2.

When

CE1

is

LOW

and

CE2

is

HIGH,

CE

is

LOW;

when

CE1

is

HIGH

or

CE2

is

LOW,

17. The device is continuously selected. OE, CE = VIL, BHE, BLE or both = VIL.

18. WE is HIGH for read cycle.

Document Number: 38-05476 Rev. *H

Page 8 of 17

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