CY7C1061DV33 Просмотр технического описания (PDF) - Cypress Semiconductor

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CY7C1061DV33

16-Mbit (1 M × 16) Static RAM

Cypress Semiconductor 

CY7C1061DV33

Pin Configurations (continued)

Figure 3. 48-ball VFBGA (8 × 9.5 × 1 mm) Single Chip Enable (-BV1XI) (Top View) [3, 4]

1

2

3

4

56

BLE OE A0 A1 A2 NC

A

I/O8 BHE A3 A4 CE I/O0 B

I/O9 I/O10 A5 A6 I/O1 I/O2 C

VSS I/O11 A17 A7 I/O3 VCC D

VCC I/O12 NC A16 I/O4 VSS E

I/O14 I/O13 A14 A15 I/O5 I/O6 F

I/O15 A19 A12 A13 WE I/O7 G

A18 A8 A9 A10 A11 NC

H

Figure 4. 54-pin TSOP II (22.4 × 11.84 × 1.0 mm) (Top View) [3]

I/O12

1

VCC

2

I/O13

3

I/O14

4

VSS

5

I/O15

6

A4

7

A3

8

A2

9

A1 10

A0 11

BHE 12

CE1 13

VCC 14

WE 15

CE2 16

A19 17

A18 18

A17 19

A16 20

A15 21

I/O0 22

VCC 23

I/O1 24

I/O2 25

VSS 26

I/O3 27

54 I/O11

53

VSS

52 I/O10

51 I/O9

50

VCC

49 I/O8

48 A5

47 A6

46 A7

45 A8

44

A9

43 NC

42 OE

41

VSS

40 NC

39 BLE

38

A10

37

A11

36

A12

35

A13

34

A14

33

I/O7

32

VSS

31

I/O6

30

I/O5

29

VCC

28

I/O4

Notes

3. NC pins are not connected on the die.

4. In BV1XI package, ball A6 is NC, ball H6 is NC and ball G2 is MSB address A19. BV1XI package has only single Chip Enable (CE).

Document Number: 38-05476 Rev. *H

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