CY7C1061DV33-10BV1XI Просмотр технического описания (PDF) - Cypress Semiconductor

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производитель

CY7C1061DV33-10BV1XI

16-Mbit (1 M × 16) Static RAM

Cypress Semiconductor 

CY7C1061DV33

Selection Guide

Description

-10

Maximum access time

10

Maximum operating current

175

Maximum CMOS standby current

25

Pin Configurations

Figure 1. 48-ball VFBGA (8 × 9.5 × 1 mm) Dual Chip Enable (-BVXI) (Top View) [1, 2]

1

2

3

4

5

6

BLE OE A0 A1 A2 CE2

A

I/O8 BHE A3 A4 CE1 I/O0

B

I/O9 I/O10 A5 A6 I/O1 I/O2 C

VSS I/O11 A17 A7 I/O3 VCC

D

VCC I/O12 NC A16 I/O4 VSS

E

I/O14 I/O13 A14 A15 I/O5 I/O6

F

I/O15 NC A12 A13 WE I/O7 G

A18 A8

A9 A10 A11 A19

H

Figure 2. 48-ball VFBGA (8 × 9.5 × 1 mm) Dual Chip Enable (-BVJXI) (Top View) [1, 2]

1

2

3

4

56

BLE OE A0 A1 A2 CE2

A

I/O8 BHE A3 A4 CE1 I/O0 B

I/O9 I/O10 A5 A6 I/O1 I/O2 C

VSS I/O11 A17 A7 I/O3 VCC

D

VCC I/O12 NC A16 I/O4 VSS

E

I/O14 I/O13 A14 A15 I/O5 I/O6

F

I/O15 A19 A12 A13 WE I/O7 G

A18 A8 A9 A10 A11 NC

H

Unit

ns

mA

mA

Notes

1. NC pins are not connected on the die.

2. In BVXI package, ball H6 is MSB address A19 and ball G2 is NC; in BVJXI package, ball H6 is NC and ball G2 is MSB address A19.

Document Number: 38-05476 Rev. *H

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