CY7C1061DV33-10BVJXIT Просмотр технического описания (PDF) - Cypress Semiconductor

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CY7C1061DV33-10BVJXIT

16-Mbit (1 M × 16) Static RAM

Cypress Semiconductor 

CY7C1061DV33

16-Mbit (1 M × 16) Static RAM

16-Mbit (1 M × 16) Static RAM

Features

■ High speed

❐ tAA = 10 ns

■ Low active power

❐ ICC = 175 mA at 100 MHz

■ Low CMOS standby power

❐ ISB2 = 25 mA

■ Operating voltages of 3.3 ± 0.3 V

■ 2.0 V data retention

■ Automatic power down when deselected

■ TTL compatible inputs and outputs

■ Easy memory expansion with CE1 and CE2 features

■ Available in Pb-free 54-pin TSOP II and 48-ball VFBGA

packages

■ Offered in single CE and dual CE options

Functional Description

The CY7C1061DV33 is a high performance CMOS Static RAM

organized as 1,048,576 words by 16 bits.

To write to the device, take Chip Enables (CE1 LOW and CE2

HIGH) and Write Enable (WE) input LOW. If Byte Low Enable

(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is

written into the location specified on the address pins (A0 through

A19). If Byte High Enable (BHE) is LOW, then data from I/O pins

(I/O8 through I/O15) is written into the location specified on the

address pins (A0 through A19).

To read from the device, take Chip Enables (CE1 LOW and CE2

HIGH) and Output Enable (OE) LOW while forcing the Write

Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data

from the memory location specified by the address pins appears

on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from

memory appears on I/O8 to I/O15. See Truth Table on page 11

for a complete description of Read and Write modes.

The input or output pins (I/O0 through I/O15) are placed in a high

impedance state when the device is deselected (CE1 HIGH/CE2

LOW), the outputs are disabled (OE HIGH), the BHE and BLE

are disabled (BHE, BLE HIGH), or during a write operation (CE1

LOW, CE2 HIGH, and WE LOW).

The CY7C1061DV33 is available in a 54-pin TSOP II package

with center power and ground (revolutionary) pinout, and 48-ball

VFBGA packages.

Logic Block Diagram

INPUT BUFFER

A0

A1

A2

AA34

AA56

1M x 16

ARRAY

AAA789

I/O0 – I/O7

I/O8 – I/O15

COLUMN

DECODER

BHE

WE

CE2

OE

CE1

BLE

Cypress Semiconductor Corporation • 198 Champion Court

Document Number: 38-05476 Rev. *H

• San Jose, CA 95134-1709 • 408-943-2600

Revised October 19, 2011

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