CY7C1061DV33-10ZXI(2006) Просмотр технического описания (PDF) - Cypress Semiconductor

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производитель

CY7C1061DV33-10ZXI
(Rev.:2006)

16-Mbit (1M x 16) Static RAM

Cypress Semiconductor 

Switching Waveforms (continued)

Read Cycle No. 2(OE Controlled)[13,14]

PRELIMINARY

CY7C1061DV33

ADDRESS

tRC

CE1

CE2

OE

BHE, BLE

tACE

tDOE

tLZOE

tDBE

tLZBE

DATA OUT

VCC

SUPPLY

CURRENT

HIGH IMPEDANCE

tLZCE

tPU

50%

Write Cycle No. 1(CE Controlled)[15,16,17]

tHZOE

DATA VALID

tHZCE

tHZBE

HIGH

IMPEDANCE

tPD

50%

IICCCC

ISB

tWC

ADDRESS

CE

tSA

tSCE

WE

BHE, BLE

DATAI/O

tAW

tPWE

tBW

tSD

Notes:

14. Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH.

15. Data I/O is high-impedance if OE or BHE and/or BLE = VIH.

16. If CE1 goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.

17. CE is a shorthand combination of both CE1 and CE2 combined. It is active LOW.

Document #: 38-05476 Rev. *C

tHA

tHD

Page 6 of 10

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