CXD2507AQ Просмотр технического описания (PDF) - Sony Semiconductor

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CXD2507AQ

CD Digital Signal Processor

Sony Semiconductor 

CXD2507AQ

1-2. Description of SENS Output

The following signals are output from SENS, depending on the microcomputer serial register value (latching

not required).

Microcomputer serial register SENS

value (latching not required) output

Meaning

$0X, 1X, 2X, 3X

SEIN SEIN, a signal input to the CXD2507 from the SSP, is output.

$4X

XBUSY Low while the auto sequencer is in operation, high when operation terminates.

$5X

FOK Oinuptuptu. ts the signal input to the FOK pin. Normally, FOK (from RF) is

High for "focus OK".

$6X

SEIN SEIN, a signal input to CXD2507 from the SSP, is output.

$AX

GFS High when the played back frame sync is obtained with the correct

timing.

$EX

$7X, 8X, 9X, BX, CX,

DX, FX

OV64

Low

Low when the EFM signal, after passing through the sync detection filter,

is lengthened by 64 channel clock pulses or more.

The SENS pin is fixed low.

Note that the SENS output can be read from the SQSO pin when SL1=1 and SL0=0. (See the $BX

commands.)

2. Subcode Interface

This section explains the subcode interface.

There are two methods for reading out a subcode externally. The 8-bit subcodes P to W can be read from

SBSO by inputting EXCK to the CXD2507.

Sub Q can be read out after the CRC check of the 80 bits of information in the subcode frame. This

accomplished, after checking SCOR and CRCF, by inputting 80 clock pulses to SQCK and reading data from

SQSO pin.

2-1. P to W Subcode Read

Data can be read out by inputting EXCK immediately after WFCK falls. (See Fig. 2-1.)

Also, SBSO can be read out from SQSO pin when SL1 = 0 and SL0 = 1. (See the $BX commands.)

2-2. 80-bit Sub Q Read

Fig. 2-2 shows the peripheral block of the 80-bit Sub Q register.

• First, Sub Q, regenerated at one bit per frame, is input to the 80-bit serial/parallel register and the CRC check

circuit.

• 96-bit Sub Q is input, and if the CRC is OK, it is output to SQSO with CRCF = 1. In addition, the 80 bits are

loaded into the parallel/serial register.

When SQSO goes high 400µs or more later (monostable multivibrator time constant) after the subcode is

read out, the CPU determines that new data (which passed the CRC check) has been loaded.

• In the CXD2507, when 80-bit data is loaded, the order of the MSB and LSB is inverted for each byte. As a

result, although the sequence of bytes is the same, the bits within the bytes are now ordered LSB first.

• Once the fact that the 80-bit data has been loaded is confirmed, SQCK is input so that the data can be read.

In the CXD2507, the SQCK input is detected, and the retriggerable monostable multivibrator for low is reset.

• The retriggerable monostable multivibrator has a time constant from 270 to 400µs. When the duration of

SQCK is high is less than this time constant, the monostable multivibrator is kept reset; during this interval,

the S/P register is not loaded into the P/S register.

• While the monostable multivibrator is being reset, data can not be loaded in the 80-bit parallel/serial register.

In other words, while reading out with a clock cycle shorter than the monostable multivibrator time constant,

the register will not be rewritten by CRCOK and others.

• Fig. 2-3 shows Timing Chart.

• Although a clock is input from SQCK pin to actually perform these operations, the high and low intervals for

this clock should be between 750ns and 120µs.

– 20 –

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