CXD2507AQ Просмотр технического описания (PDF) - Sony Semiconductor

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Компоненты Описание

производитель

CXD2507AQ

CD Digital Signal Processor

Sony Semiconductor 

CXD2507AQ

$DX commands

Command

CLV CTRL

D3

D2

DCLV

PWM MD

TB

D1

D0

TP

CLVS

Gain

See the $CX command.

Command bit

Explanation (See Timing Chart 1-5.)

DCLV PWM MD = 1 CLV PWM mode specified. Both MDS and MDP are used.

DCLV PWM MD = 0 CLV PWM mode specified. Ternary MDP values are output.

Command bit

TB = 0

TB = 1

TP = 0

TP = 1

Explanation

Bottom hold in CLVS mode at cycle of RFCK/32

Bottom hold in CLVS mode at cycle of RFCK/16

Peak hold in CLVS mode at cycle of RFCK/4

Peak hold in CLVS mode at cycle of RFCK/2

$EX commands

Command

CLV mode

D3

CM3

D2

CM2

D1

CM1

D0

CM0

CM3 CM2 CM1 CM0

Mode

Explanation

0

0

0

0

STOP

See Timing Chart 1-6.

1

0

0

0

KICK

See Timing Chart 1-9.

1

0

1

0

BRAKE

See Timing Chart 1-8.

1

1

1

0

CLVS

1

1

1

1

CLVP

0

1

1

0

CLVA

STOP

KICK

BRAKE

CLVS

CLVP

CLVA

: Spindle motor stop mode

: Spindle motor forward rotation mode

: Spindle motor reverse rotation mode

: Rough servo mode. When RF-PLL circuit lock is disengaged, this mode is used to pull the disc

rotations within the RF-PLL capture range.

: PLL servo mode.

: Automatic CLVS/CLVP switching mode. This mode is normally used during playback.

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