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STM6321YWY6F(2008) Просмотр технического описания (PDF) - STMicroelectronics

Номер в каталоге
Компоненты Описание
производитель
STM6321YWY6F
(Rev.:2008)
ST-Microelectronics
STMicroelectronics ST-Microelectronics
STM6321YWY6F Datasheet PDF : 28 Pages
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Operation
2
Operation
STM6321/6322STM6821/6822/6823/6824/6825
2.1
Reset output
The STM6xxx Supervisor asserts a reset signal to the MCU whenever VCC goes below the
reset threshold (VRST), a watchdog time-out occurs, or when the Push-button Reset Input
(MR) is taken low. Reset is guaranteed valid for VCC < VRST down to VCC =1 V for TA = 0°C
to 85°C.
During power-up, once VCC exceeds the reset threshold an internal timer keeps reset low
for the reset time-out period, trec. After this interval reset is de-asserted.
Each time RST is asserted, it stays low for at least the reset time-out period (trec). Any time
VCC goes below the reset threshold the internal timer clears. The reset timer starts when
VCC returns above the reset threshold.
2.2
Open drain RST output
The STM6321/6322/6822 have an active-low, open drain reset output. This output structure
will sink current when RST is asserted. Connect a pull-up resistor from RST to any supply
voltage up to 6 V (see Figure 11). Select a resistor value large enough to register a logic
low, and small enough to register a logic high while supplying all input current and leakage
paths connected to the reset output line. A 10 kΩ pull-up resistor is sufficient in most
applications.
Figure 11. STM6321/6322/6822 open drain RST output with multiple supplies
3.3V
VCC
STM6XXX
10k
MR(1)
WDI(2)
RST(3)
RST
GND
5.0V
5V System
AI09137
1. STM6322/6822
2. STM6321/6822
3. STM6321/6322
10/28

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