LC72711LW Просмотр технического описания (PDF) - SANYO -> Panasonic

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производитель

LC72711LW

Mobile FM Multiplex Broadcast (DARC) Receiver IC

SANYO -> Panasonic 

Block Diagram

LC72711W, 72711LW

Vddd

Vssd

STNBY

RST

XOUT

XIN

MPXIN

Vdda

Vssa

LPF

7.2MHz

1T delay

2T delay

Clock

regeneration

LPF

MSK correction

circuit

Synchronization

regeneration

PN decoding

Timing

control

Error correction:

layer 2 CRC

Data

Anti-aliasing

filter

Vref

Vref

76kHz

BPF

(SCF)

Output control (CPU interface) and

layer 4 CRC detection circuit

Address

Memory array

Pin Functions

Pin No.

3

Pin

IOCNT1

4

IOCNT2

13

DACK

38

WR

39

RD

40

A0/CL

41

A1/CE

42

A2/DI

43

A3

44

CS

46

RST

45

STNBY

47

SP

48

BUSWD

60

TEST

58

TPC1

59

TPC2

61

TOSEL1

62

TOSEL2

49

TIN

5

CLK16

6

DATA

9

FCK

10

BCK

7

FLOCK

8

BLOCK

11

CRC4

33

INT

12

DREQ

16

RDY

Function

Data bus I/O control 1 (SP=low)*1

Data bus I/O control 2 (SP=low)*1

DMA acknowledge (SP=low)*1

Write control signal (SP=low)*1

Read control signal (SP=low)*1

Address input 0 (SP=low) CCB CL input (SP=High)

1 (SP=low) CCB CE input (SP=High)

2 (SP=low) CCB DI input (SP=High)

3 (SP=low)*1

Chip select input (SP=L)*1

System reset input (negative logic)

Standby mode (positive logic)

SP=low: parallel, SP=high: serial

BUSWD=low: 8 bits, BUSWD=high: 16bits

The test pin must be connected to the digital system ground (VSS).

Must be connected to the digital system power supply (VDD) or ground

(VSS) in normal operation.

As above

As above

As above

As above

Clock regeneration monitor

Demodulated data monitor

Frame start signal output

Block start signal output

Outputs a high level during frame synchronization

Outputs a high level during block synchronization

Level 4 CRC detection result output

External CPU interrupt request output

DMA request signal

Read ready signal

I/O

Input

Input

Output

Pin circuit

Continued on next page.

No.6167-6/26

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