LC72711LW Просмотр технического описания (PDF) - SANYO -> Panasonic
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LC72711LW Datasheet PDF : 26 Pages
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LC72711W, 72711LW
Continued from preceding page.
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
RDY width (corrected output read)
tWDRDY
RDY (BUSWD=L 8bits)
RDY ((BUSWD=H 16bits)
60
210 nS
300
490 nS
DACK to DREQ delay
DMA cycle wait
RD low-level width (DMA)
tDREQ
tCYDM
tWRDM
DREQ, DACK
RD, DREQ
RD
260 nS
420 nS
300
nS
Notes: Application designs must take the RDY signal output delay into consideration if the RDY signal is used as the CPU bus wait signal.
If the RDY signal is not used, (that is, if no wait states are inserted) the value of the RD low-level width will be 250ns (minimum).
[LC72711LW]
Allowable Operating Ranges at Ta=-40 to +85°C, VSS=0V
Parameter
Supply voltage
High-level input voltage
Low-level input voltage
Oscillator frequency
XIN input sensitivity
Input amplitude
[Serial I/O]
Clock low-level period
Clock high-level period
Data setup time
Data hold time
CE wait time
CE setup time
CE hold time
Data latch change time
Data output time
CRC4 change time
Symbol
VDD
VIH1
VIH2
VIL1
VIL2
FOSC
VXI
VMPX1
VMPX2
Conditions
A0/CL, A1/CE, A2/DI, RST, STNBY
DACK, WR, RD, CS, SP, BUSWD, A3, IOCNT1, IOCNT2
Pins for which VIH1 applies
Pins for which VIH2 applies
This IC operates with a frequency precision of ±250 ppm
With a sine wave input to XIN, capacitor coupling,
VDD=+2.7 to +3.6V
With a 100% modulated composite signal input to
MPXIN, VDD=+3.3V
With a 100% modulated composite signal input to
MPXIN, VDD=+2.7V
min
2.7
0.7VDD
0.7VDD
VSS
VSS
400
120
120
Ratings
typ
7.2
max
3.6
5.5
VDD
0.3VDD
0.3VDD
Unit
V
V
V
V
V
MHz
900 mVrms
350 mVrms
180 mVrms
tCL
tCH
tSU
tHD
tEL
tES
tEH
tLC
tDDO
tCRC
A0/CL
A0/CL
A0/CL, A2/DI
A0/CL, A2/DI
A0/CL, A1/CE
A0/CL, A1/CE
A0/CL, A1/CE
A1/CE
DO, A0/CL
CRC4, A0/CL
0.7
µS
0.7
µS
0.7
µS
0.7
µS
0.7
µS
0.7
µS
0.7
µS
0.7 µS
277
555 nS
0.7 µS
[LC72711LW]
Allowable Operating Ranges: Parallel Interface at Ta=-40 to +85°C, VSS=0V
Parameter
[Parallel I/O]
Address to RD setup
RD to address hold
RD low-level width
RD low-level width (when RDY is used)
RD cycle wait
RDY width (Register read)
RD data hold
Address to WR setup
WR to address hold
WR cycle wait
WR low-level width
WR data hold
RDY output delay
Corrected output RD width
Corrected output RD width
(when RDY is used)
RDY width (corrected output read)
DACK to DREQ delay
Symbol
Conditions
Ratings
Unit
min
typ
max
tSARD
A0/CL, A1/CE, A2/DI, A3, RD
20
tHARD
A0/CL, A1/CE, A2/DI, A3, RD, tWRDL=>250ns
-20
tWRDL1 RD
280
tWRDL2 RD
100
tCYRD
A0/CL, A1/CE, A2/DI, A3, RD
150
tWRDY RDY
60
tRDH
RD, DATn
0
tSAWR A0/CL, A1/CE, A2/DI, A3, WR
20
tHAWR A0/CL, A1/CE, A2/DI, A3, WR
20
tCYWR A0/CL, A1/CE, A2/DI, A3, WR
150
tWWRL WR
200
tWDH
WR, DATn
0
tDRDY
RD, RDY
0
RD (BUSWD=L 8bits)
300
tWDRD1 RD (BUSWD=H 16bits)
540
RD (BUSWD=L 8bits)
100
tWDRD2 RD (BUSWD=H 16bits)
300
RDY (BUSWD=L 8bits)
60
tWDRDY RDY ((BUSWD=H 16bits)
300
tDREQ
DREQ, DACK
nS
nS
nS
nS
nS
230 nS
nS
nS
nS
nS
nS
nS
50 nS
nS
nS
nS
nS
230 nS
490 nS
260 nS
Continued on next page.
No.6167-3/26
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