SST30VR021 Просмотр технического описания (PDF) - Silicon Storage Technology
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SST30VR021 Datasheet PDF : 12 Pages
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2 Mbit ROM + 1 Mbit / 2Mbit / 256 Kbit SRAM
ROM/RAM Combo
SST30VR021 / SST30VR022 / SST30VR023
Data Sheet
PACKAGING DIAGRAMS
Pin # 1 Identifier
1.05
0.95
8.10
7.90
.50
BSC
.270
.170
12.50
12.30
0.15
0.05
0.70
0.50
14.20
13.80
32.TSOP-WH-ILL.4
Note:
1. Complies with JEDEC publication 95 MO-142 BA dimensions, although some dimensions may be more stringent.
2. All linear dimensions are in millimeters (min/max).
3. Coplanarity: 0.1 (±.05) mm.
4. Maximum allowable mold flash is 0.15mm at the package ends, and 0.25mm between leads.
32-PIN THIN SMALL OUTLINE PACKAGE (TSOP) 8MM X 14MM
SST PACKAGE CODE: WH
©2001 Silicon Storage Technology, Inc.
11
S71135-02-000 4/01 380
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