SP8855E Просмотр технического описания (PDF) - Unspecified
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SP8855E Datasheet PDF : 14 Pages
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SP8855E
40k 40k 5k
Vcc
5k
INPUT
50µA
0V
Figure 7a - RF and reference divider programming bits,
F F enable, control direction and phase detector gain
pd/ ref
control inputs
C-LOCK DETECT (HIGH WHEN LOCKED)
18
Vcc
3k
3k
50k
V REF
4.7V
20µA
100µA
0V
Figure 7c - Lock detect decouple
R set
19
Vcc
CHARGE PUMP
CURRENT SOURCES
130
Vcc
4k
325
325
RF
INPUT13
500
500
RF
INPUT14
3mA
3k
0V
Figure 7b - RF inputs
Vcc
2k5
2k5
400µA
LOW
WHEN
LOCKED 17
3k
3k
LOCK
DETECT
OUTPUT
100
100
1k 11
0V
Figure 7d - Lock detect output
CHARGE PUMP
OUTPUT
REFERENCE
Vcc
20 21
450
450
UP
83
83
Vcc
DOWN
2mA
Figure 7e - Rset pin
Figure 7f - Charge pump circuit
Figure 7 - Interface circuit diagrams
Data Sheet 291297 issue 3
8
Plessey Semiconductors Ltd.
Design & Technology Centre, Delta 500, Delta Business Park, Great Western Way, Swindon, UK SN5 7XE
Tel: +44 1793 518000
Fax: +44 1793 518030
Web: www.plesseysemi.com
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