SP8855E Просмотр технического описания (PDF) - Unspecified

Номер в каталоге

Компоненты Описание

производитель

SP8855E

2.8GHz Parallel Load Professional Synthesiser

Unspecified 

SP8855E

PIN Description

PIN

Description

1,2,3,4,5,6,7,8,9,10,11,42,43,44

These pins are the data inputs used to set the RF divider ratio

(M.N+A). Open circuit = 1 (high) on these pins. Inputs are transparent into

the data buffers.

13, 14 (RF INPUT)

Balanced inputs to the RF pre-amplifier. For single ended operation the

signal is AC coupled into pin 13 with pin 14 AC decoupled to ground (or

vice -versa). Pins 13 and 14 are internally DC biased.

17 (LOCK DETECT INPUT)

A current sink into this pin is enabled when the lock detect circuit indicates

lock. Used to give an external indication of phase lock.

18 (C-LOCK DETECT)

A capacitor connected to this point determines the lock detect integrator time

constant and can be used to vary the sensitivity of the phase lock indicator.

19 (Rset)

20 (CP OUTPUT)

An external resistor from Pin 19 to VCC sets the charge pump output current

The phase detector output is a single ended charge pump sourcing or

sinking current to the inverting input of an external loop filter.

21 (CP REF)

Connected to the non-inverting input of the loop filter to set the optimum DC

bias.

22 (F /F ENABLE

ref pd

Part of the data input bus. When this pin is logic HI the F and F outputs

ref

pd

are enabled. Open circuit = HI

23 (CONTROL DIRECTION)

This pin controls charge pump output direction. For Pin 23 HI the output

sinks current when Fpd > Fref or when the RF phase leads Ref phase. For Pin

23 LO the relationship is reversed. (see table 2).

Changing the state of pin 23 reverses the pins on which Fref and Fpd output

occur. See pin 24 and Pin 25 below for details. Open circuit = HI.

24 = F if Pin 23 is HI

pd

= Fref if Pin 23 is LO

25 = F if Pin 23 is HI

ref

RF divider output pulses. Fpd = RF input frequency /(M.N+A). Pulse width =

8 RF input cycles (1 cycle of the divide by 8 prescaler output).

Reference divider output pulses. Fref = Reference input frequency/R. Pulse

width = high period of Ref input.

27 (Reference Oscillator Capacitor)

Leave open circuit if an external reference is used. See fig. 5 for typical

connection for use as an onboard crystal oscillator.

28 (Ref IN/XTAL)

This pin is the input buffer amplifier for an external reference signal. This

amplifier provides the active element if an onboard crystal oscillator is used.

29,30,31,32,33,34,35,36,37,38

These pins set the Reference divider ratio R. Open circuit = HI.

39 (Phase Detector ENABLE)

When this pin is HI the phase detector output is enable. Open circuit = HI.

40, 41 (PD Gain)

These pins set the charge pump current multiplication factor (see table 1).

Open circuit = HI.

Data Sheet 291297 issue 3

3

Plessey Semiconductors Ltd.

Design & Technology Centre, Delta 500, Delta Business Park, Great Western Way, Swindon, UK SN5 7XE

Tel: +44 1793 518000

Fax: +44 1793 518030

Web: www.plesseysemi.com

Share Link: