MT90500 Просмотр технического описания (PDF) - Zarlink Semiconductor Inc

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MT90500

Multi-Channel ATM AAL1 SAR

Zarlink Semiconductor Inc 

MT90500

List of Figures

Figure 1 - MT90500 Block Diagram...................................................................................................................12

Figure 2. Pin Connections ................................................................................................................................26

Figure 3 - TDM Clock Selection and Generation Logic .....................................................................................29

Figure 4 - TDM Frame Buffer to External Memory Transfer..............................................................................33

Figure 5 - Transmit Circular Buffer Control Structure ........................................................................................34

Figure 6 - External Memory to TDM Frame Buffer Transfer..............................................................................35

Figure 7 - External Memory to Internal Memory Control Structure....................................................................37

Figure 8 - Memory Read Pipeline Length..........................................................................................................38

Figure 9 - Logical Byte Address vs. Physical Address and Memory Banks ......................................................39

Figure 10 - Read / Write Turnaround Cycles.......................................................................................................40

Figure 11 - Read / Read Turnaround Cycles.......................................................................................................41

Figure 11 - Read / Write turnaround Cycles ........................................................................................................41

Figure 12 - AAL1 ATM Cell Format .....................................................................................................................42

Figure 13 - Partially-Filled AAL1 and CBR-AAL0 Cell Formats...........................................................................43

Figure 14 - CBR-AAL5 Cell Format ....................................................................................................................44

Figure 15 - Transmit Event Scheduler.................................................................................................................49

Figure 17 - Transmit Control Structure Format (CBR-AAL5)...............................................................................50

Figure 16 - Transmit Control Structure Format (AAL1 & CBR-AAL0) .................................................................51

Figure 18 - a: Sample Three-Channel Transmit Control Structure (AAL1/CBR-AAL0) .......................................53

Figure 18 - b: Sample One-Channel Transmit Control Structure (CBR-AAL5) ...................................................53

Figure 19 - Overview of CBR Data Transmission Process..................................................................................54

Figure 20 - VC Pointer For Scheduler-Controlled Non-CBR Data Cell ...............................................................55

Figure 21 - Transmit Non-CBR Data Cell Structure Format ................................................................................56

Figure 22 - RX_SAR Control Structure................................................................................................................58

Figure 23 - Overrun and Underrun Situations .....................................................................................................60

Figure 24 - MT90500 Daisy Chain Example........................................................................................................62

Figure 25 - Mux and Internal FIFO Sub-Module Block Diagram .........................................................................63

Figure 26 - Receive Cell Selection Process ........................................................................................................65

Figure 27 - MT90500 Cell Receive Process........................................................................................................66

Figure 28 - Look-up Table Non-CBR Data Entry.................................................................................................67

Figure 29 - Received Non-CBR Data Cell Internal Format..................................................................................68

Figure 30 - Overview of CBR Data Reception Process.......................................................................................69

Figure 31 - Adaptive Clock Recovery Sub-Module (Simplified Functional Block Diagram).................................70

Figure 32 - Timing Reference Cell Processing State Machine............................................................................71

Figure 33 - Transmit SRTS Operation.................................................................................................................73

Figure 34 - Receive SRTS Operation..................................................................................................................74

Figure 35 - Clock Recovery Using SRTS Method (Hardware) ............................................................................75

Figure 36 - Clock Recovery Using SRTS Method (CPU) ....................................................................................76

Figure 37 - A Typical JTAG Test Connection ......................................................................................................79

Figure 38. MT90500 Interrupt Structure .............................................................................................................81

Figure 39 - Nominal TDM Bus Timing ...............................................................................................................114

Figure 40 - Main TDM Bus Output Clocking Parameters - Positive Frame Pulse .............................................115

Figure 41 - Main TDM Bus Output Clocking Parameters - Negative Frame Pulse ...........................................115

Figure 42 - Main TDM Bus - Serial Output Timing ............................................................................................116

Figure 43 - Main TDM Bus - 2/4 Sampling ........................................................................................................118

Figure 44 - Main TDM Bus - 3/4 Sampling ........................................................................................................118

Figure 45 - Main TDM Bus - 4/4 Sampling ........................................................................................................119

Figure 46 - Local TDM Bus Output Parameters - Positive Frame Pulse ...........................................................121

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