HUFA76413DK8T_F085 Просмотр технического описания (PDF) - Fairchild Semiconductor
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HUFA76413DK8T_F085 Datasheet PDF : 11 Pages
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Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, TJM, and the
thermal resistance of the heat dissipating path determines
the maximum allowable device power dissipation, PDM, in an
application.
Therefore the application’s ambient
temperature, TA (oC), and thermal resistance RθJA (oC/W)
must be reviewed to ensure that TJM is never exceeded.
Equation 1 mathematically represents the relationship and
serves as the basis for establishing the rating of the part.
PDM
=
(---T---J----M------–-----T---A----)-
RθJA
(EQ. 1)
In using surface mount devices such as the SO-8 package,
the environment in which it is applied will have a significant
influence on the part’s current and maximum power
dissipation ratings. Precise determination of PDM is complex
and influenced by many factors:
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
300
ln RθJA = 103.2 - 24.3 * (AREA)
250
228 oC/W - 0.006in2
200
191 oC/W - 0.027in2
150
100
50
Rθβ = 46.4 - 21.7 * ln(AREA)
0
0.001
0.01
0.1
1
AREA, TOP COPPER AREA (in2) PER DIE
Figure 22. Thermal Resistance vs Mounting
Pad Area
2. The number of copper layers and the thickness of the
board.
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
Fairchild provides thermal information to assist the
designer’s preliminary application evaluation. Figure 22
defines the RθJA for the device as a function of the top
copper (component side) area. This is for a horizontally
positioned FR-4 board with 1oz copper after 1000 seconds
of steady state power with no air flow. This graph provides
the necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Fairchild device
Spice thermal model or manually utilizing the normalized
maximum transient thermal impedance curve.
Thermal resistances corresponding to other copper areas
can be obtained from Figure 22 or by calculation using
Equation 2. The area, in square inches is the top copper
area including the gate and source pads.
RθJA = 103.2 – 24.3 ln (Area)
(EQ. 2)
The dual die SO-8 package introduces an additional thermal
coupling resistance, RθB. Equation 3 describes RθB as a
function of the top copper mouting pad area.
RθB = 46.4 – 21.7 ln (Area)
(EQ. 3)
The thermal coupling resistance vs. copper area is also
graphically depicted in Figure 22.
HUFA76413DK8T_F085 Rev. C1
7
www.fairchildsemi.com
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