75829D Просмотр технического описания (PDF) - Fairchild Semiconductor
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производитель
75829D Datasheet PDF : 10 Pages
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HUF75829D3, HUF75829D3S
SABER Electrical Model
REV 4 January 2000
template huf75829 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (is = 8.80e-13, rs=1.05e-2, xti=5, trs1=2.20e-3, trs2=3.70e-6, cjo = 1.04e-9, tt = 9.90e-8, m = 0.55)
dp..model dbreakmod = (rs=1.05, trs1=1.80e-3, trs2=3.00e-6)
dp..model dplcapmod = (cjo = 1.30e-9, is = 1e-30, m = 0.82)
m..model mmedmod = (type=_n, vto = 3.22, kp = 5, is = 1e-30, tox = 1)
m..model mstrongmod = (type=_n, vto = 3.67, kp = 53, is = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 2.78, kp = 0.10, is = 1e-30, tox = 1)
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -5.8, voff = -2.4)
sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -2.4, voff = -5.8)
DPLCAP 5
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -1.8, voff = 0.5)
10
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.5, voff = -1.8)
RSLC1
c.ca n12 n8 = 1.70e-9
c.cb n15 n14 = 1.70e-9
c.cin n6 n8 = 9.90e-10
RSLC2
51
ISCL
LDRAIN
DRAIN
2
RLDRAIN
dp.dbody n7 n5 = model=dbodymod
-
50
DBREAK
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod
i.it n8 n17 = 1
l.ldrain n2 n5 = 1e-9
l.lgate n1 n9 = 3.11e-9
l.lsource n3 n7 = 3.72e-9
GATE
1
ESG
6
8
RDRAIN
+
EVTHRES
16
+ 19 - 21
LGATE
EVTEMP
8
RGATE + 18 - 6
9
20 22
MMED
RLGATE
MSTRO
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
CIN
8
11
MWEAK
EBREAK
+
17
18
-
7
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
RSOURCE
DBODY
LSOURCE
SOURCE
3
RLSOURCE
res.rbreak n17 n18 = 1, tc1 = 1.10e-3, tc2 = -3.00e-7
res.rdrain n50 n16 = 6.22e-2, tc1 = 9.40e-3, tc2 = 2.70e-5
res.rgate n9 n20 = 2.13
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 31.1
res.rlsource n3 n7 = 37.2
res.rslc1 n5 n51 = 1e-6, tc1 = 4.10e-3, tc2 = 4.00e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 1.88e-2, tc1 = 1e-3, tc2 = 1e-6
res.rvtemp n18 n19 = 1, tc1 = -2.60e-3, tc2 = -1.00e-6
res.rvthres n22 n8 = 1, tc1 = -2.40e-3, tc2 = -7.50e-6
S1A
12 13
8
S2A
14
15
13
S1B
S2B
CA
13
CB
+
+ 14
EGS
6
8
-
EDS
5
8
-
RBREAK
17
18
RVTEMP
19
IT
-
VBAT
+
8
22
RVTHRES
spe.ebreak n11 n7 n17 n18 = 156.5
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/36))** 3))
}
}
©2001 Fairchild Semiconductor Corporation
HUF75829D3, HUF75829D3S Rev. B
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