74LVC541AM Просмотр технического описания (PDF) - STMicroelectronics

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74LVC541AM

OCTAL D-TYPE LATCH HIGH PERFORMANCE

STMicroelectronics 

s 5V TOLERANT INPUTS

s HIGH SPEED: tPD = 4.2ns (MAX.) at VCC = 3V

s POWER DOWN PROTECTION ON INPUTS

AND OUTPUTS

s SYMMETRICAL OUTPUT IMPEDANCE:

|IOH| = IOL = 24mA (MIN) at VCC = 3V

s PCI BUS LEVELS GUARANTEED AT 24 mA

s BALANCED PROPAGATION DELAYS:

tPLH ≅ tPHL

s OPERATING VOLTAGE RANGE:

VCC(OPR) = 1.65V to 3.6V (1.2V Data

Retention)

s PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 541

s LATCH-UP PERFORMANCE EXCEEDS

500mA (JESD 17)

s ESD PERFORMANCE:

HBM > 2000V (MIL STD 883 method 3015);

MM > 200V

DESCRIPTION

The 74LVC541A is a low voltage CMOS OCTAL

BUS BUFFER (3-STATE) fabricated with

sub-micron silicon gate and double-layer metal

wiring C2MOS tecnology. It is ideal for 1.65 to 3.6

VCC operations and low power and low noise

applications.

The 3 STATE control gate operates as two input

AND such that if either G1 or G2 are high, all eight

outputs are in the high impedance state.

PIN CONNECTION AND IEC LOGIC SYMBOLS

74LVC541A

OCTAL D-TYPE LATCH

HIGH PERFORMANCE

PRELIMINARY DATA

SOP

TSSOP

ORDER CODES

PACKAGE

TUBE

SOP

TSSOP

74LVC541AM

T&R

74LVC541AMTR

74LVC541ATTR

In order to enhance PC board layout, the

74LVC541A offers a pinout having inputs and

outputs on opposite sides of the package.

This device is designed to interface directly High

Speed CMOS systems with TTL and NMOS

components.

It has more speed performance at 3.3V than 5V

AC/ACT family, combined with a lower power

consumption.

All inputs are equipped with protection circuits

against static discharge, giving them 2KV ESD

immunity and transient excess voltage.

February 2002

1/9

This is preliminary information on a new product now in development are or undergoing evaluation. Details subject to change without notice.

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