MTL007 Просмотр технического описания (PDF) - Myson Century Inc

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MTL007

SXGA Flat Panel Controller

Myson Century Inc 

MTL007

FUNCTIONAL DESCRIPTION

INPUT PROCESSOR

General Description

The function of Input Interface is to provide the interface between the MTL007 and external input devices. It can

process both non-interlaced and interlaced RGB graphic input, YUV video input, and digital RGB input

compliant with digital LVDS/PanelLink TMDS interface. It also contains the built-in YUV to RGB color space

converter.

i) RGB Input Format

Since the MTL007 is a low cost solution, the RGB input port can only work in Single Pixel mode (24 bits). The

R/G/BIN ports are sampled at the rising edge of the RGB input clock.

ii) TMDS Input Format

The Digital RGB input port works just in the same way as Sec 3.1.1 except one more input pin is needed: Digital

Input Enable DIEN.

With a single pixel input interface, the supported format is up to true color, including 18 bit/pixel or 24 bit/pixel.

iii) YUV Input Format

The YUV input port supports interlaced video data from the most common video decoder ICs like SAA711x. The

16 bit data bus is shared with the ports RIN[7:0] and GIN[7:0]. The 16 bit data is sampled at the rising edge of

the shared video clock VPCLK when the shared data enable HREF is active. The supported formats are

YUV4:1:1 and YUV4:2:2 with CCIR601/CCIR656 standard.

iv) Input HSYNC Path

Besides the pin HSYNC, the MTL007 provides another pin RAWHS to support Sync Processor in the MTL007.

Generally, the HSYNC generated by an ADC may have a very narrow pulse width and a different polarity from

the original HSYNC provided by the source. The RAWHS input provides the path of original HSYNC connection

to the MTL007, which makes Sync Processor in the MTL007 work correctly.

v) YUV to RGB Converter

It is used to convert YCbCr format into RGB format. The basic equations are as follows:

R = Y + 1.371(Cr - 128)

G = Y - 0.698(Cr - 128) - 0.336(Cb - 128)

B = Y + 1.732(Cb - 128)

vi) De-interlace mode

For interlace input, the MTL007 features de-interlacing algorithm for processing interlaced video data.In this

mode, two fields are toggled displayed. The missing lines are calculated from interpolating the neighbor lines.

This algorithm has an average good quality for still and moving picture.

vii) Sync Processor

The V/H SYNC processing block performs the functions of Composite signal separation/insertion, SYNC inputs

presence check, frequency counting, polarity detection and control. It contains a de-glitch circuit to filter out any

pulse shorter than one OSC period treated as noise on V/H SYNC pulses.

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