MTL007 Просмотр технического описания (PDF) - Myson Century Inc
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MTL007 Datasheet PDF : 65 Pages
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MTL007
Random Read
The operation of Random Read allows access to any address. Before reading data operation, it must issue a
“dummy write” operation — a start condition, slave address and then the word address for read. After
responding the word address acknowledge, the master generates a start condition again and slave address with
R/W bit is set to 1. The MTL007 then transmits the 8 bits of data. Upon the completion of receiving data, the
master will generate a stop condition instead of an Acknowledge as shown in Figure-9.
S
T
A
R SLAVE
T ADDRESS
SDA
WA
C
K
WORD
ADDRESS
S
T
A
R SLAVE
T ADDRESS
A
RA
C
C
K
K
S
T
O
DATA
P
Figure-9 Random Read
Sequential Read
The initial step can be as either Current Address Read or Random Read. The first read data is transmitted the
same manner as other read methods. However, the master generates an Acknowledge indicating that it
requires more data to read. The MTL007 continues to output data for each Acknowledge received. The output
data is sequential and the internal address counter increments by one for next read data as shown in Figure-10.
S
T
A
R SLAVE
T ADDRESS
SDA
RA
C
K
DATA n
DATA n+1
A
A
C
C
K
K
S
T
O
DATA n+x
P
Figure-10 Sequential Read
ii) Interrupt
The MTL007 supports one interrupt output signal (IRQ) which can be programmed to provide SYNC related or
function status related interrupts to the system. Upon receiving the interrupt request, Firmware needs to first
check the interrupt event by reading the Interrupt Flag Control registers (Reg. E8h and E9h) to decide what
events are happening. After the operation is finished, Firmware needs to clear interrupt status by writing the
same registers Reg. E8h and E9h. Furthermore, by using the Interrupt Flag Enable registers (Reg. EAh and
EBh), each interrupt event can be masked.
iii) Update Register Contents
page 15 of 65
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