M5M51008DFP Просмотр технического описания (PDF) - Renesas Electronics
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M5M51008DFP Datasheet PDF : 9 Pages
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(4) TIMING DIAGRAMS
Read cycle
A0~16
S1
S2
OE
DQ1~8
W = "H" level
(Note 5)
(Note 5)
(Note 5)
Ver. 1.1
MITSUBISHI LSIs
M5M51008DFP,VP,RV,KV,KR -55H, -70H
1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
tCR
ta(A)
ta (S1)
ta (S2)
ta (OE)
ten (OE)
ten (S1)
ten (S2)
tv (A)
tdis (S1)
tdis (S2)
tdis (OE)
DATA VALID
(Note 5)
(Note 5)
(Note 5)
Write cycle (W control mode)
tCW
A0~16
S1
S2
OE
W
DQ1~8
(Note 5)
(Note 5)
tsu (S1)
tsu (S2)
tsu (A-WH)
tsu (A)
tw (W)
trec (W)
tdis (OE)
tdis (W)
ten (W)
ten(OE)
DATA IN
STABLE
tsu (D)
th (D)
(Note 5)
(Note 5)
5
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