74ABT821D Просмотр технического описания (PDF) - NXP Semiconductors.
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74ABT821D Datasheet PDF : 16 Pages
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NXP Semiconductors
74ABT821
10-bit D-type flip-flop; positive-edge trigger; 3-state
10. Dynamic characteristics
Table 7. Dynamic characteristics
GND = 0 V; for test circuit, see Figure 8.
Symbol Parameter
Conditions
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tsu(H)
tsu(L)
th(H)
th(L)
tWH
tWL
fmax
LOW to HIGH
CP to Qn; see Figure 5
propagation delay
HIGH to LOW
CP to Qn; see Figure 5
propagation delay
OFF-state to HIGH OEn to Qn; see Figure 6
propagation delay
OFF-state to LOW OEn to Qn; see Figure 6
propagation delay
HIGH to OFF-state OEn to Qn; see Figure 6
propagation delay
LOW to OFF-state OEn to Qn; see Figure 6
propagation delay
set-up time HIGH Dn to CP; see Figure 7
set-up time LOW Dn to CP; see Figure 7
hold time HIGH
Dn to CP; see Figure 7
hold time LOW
Dn to CP; see Figure 7
pulse width HIGH CP; see Figure 5
pulse width LOW CP; see Figure 5
maximum
frequency
see Figure 5
11. Waveforms
25 °C; VCC = 5.0 V −40 °C to +70 °C; Unit
VCC = 5.0 V ± 0.5 V
Min Typ Max Min
Max
2.1 4.1 5.6 2.1
6.2 ns
2.8 4.6 6.2 2.8
6.7 ns
1.0 3.0 4.5 1.0
5.3 ns
2.2 4.1 5.6 2.2
6.3 ns
2.7 4.7 6.2 2.7
6.7 ns
2.3 4.6 6.1 2.3
6.5 ns
2.1 0.5 -
2.1
2.1 0.3 -
2.1
1.3 0 -
1.3
1.3 −0.3 -
1.3
2.9 1.8 -
2.9
3.8 2.8 -
3.8
125 185 -
125
- ns
- ns
- ns
- ns
- ns
- ns
- MHz
VI
CP input
GND
VOH
Qn output
VOL
1/fmax
VM
t WH
t WL
t PHL
VM
t PLH
001aac445
Fig 5.
VM = 1.5 V
VOL and VOH are typical voltage output levels that occur with the output load.
Propagation delay clock input (CP) to output (Qn), clock pulse (CP) width and
maximum clock (CP) frequency
74ABT821_3
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 03 — 25 February 2010
© NXP B.V. 2010. All rights reserved.
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