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ISL6131

Multiple Voltage Supervisory ICs

Renesas Electronics 

ISL6131, ISL6132

Description and Operation

The ISL6131 is a four-voltage, high-accuracy, supervisory IC

designed to monitor multiple voltages greater than 0.7V relative

to Pin 10 of the IC.

Upon VDD bias power-up, the STATUS and PGOOD outputs are

held correctly low once VDD is as low as 1V. Once biased to 1.5V,

the IC continuously monitors from one to four voltages

independently through external resistor dividers, comparing each

voltage monitoring (VMON) pin voltage to an internal 0.633V

(VVMONvth) reference.

With the EN input driven high or open, as each VMON input rises

above VVMONvth, a timer is set to ensure ~160ms of continuous

compliance. Then the related STATUS output is released to be

pulled high. The STATUS outputs are open-drain to allow OR’ing of

these signals and interfacing to a logic high level up to VDD. The

STATUS outputs are designed to reject short transients (~30s)

on the VMON inputs. Once all STATUS outputs are high, a

Power-Good (PGOOD) output signal is generated high to indicate

that all monitored voltages are greater than minimum

compliance level.

Once any VMON input falls below VVMONvth for longer than the

glitch filter time, both the PGOOD and the related STATUS output

are pulled low. The other STATUS outputs remain high as long as

their corresponding VMON voltage remains valid and the PGOOD

validation process is reset.

Figure 1 shows the ISL6131 typical application schematic, and

Figure 3 is an operational timing diagram. See Figures 10 to 17 for

ISL6131 function and performance. Figures 10 and 11 show the

VDD rising along with STATUS and PGOOD response. Figures 12

and 13 illustrate VMON falling below VVMONvth, and Figure 14

shows VMON rising above VVMONvth with STATUS and PGOOD

response. Figure 15 shows VDD failing, with STATUS and PGOOD

response. Figures 16 and 17 show ENABLE to STATUS and PGOOD

timing.

If less than four voltages are being monitored, connect the

unused VMON pins to VDD for proper operation. All unused

STATUS outputs can be left open.

The ISL6132 is a dual voltage monitor for undervoltage and

overvoltage compliance. Figure 2 shows the typical ISL6132

implementation schematic, and Figure 4 is the operational timing

diagram.

There are two pairs of monitors, each with an undervoltage

(UVMON) input and an overvoltage (OVMON) input, along with

associated STATUS and PGOOD outputs.

Upon VDD bias power-up, the STATUS and PGOOD outputs are

held correctly low, once VDD is as low as 1V. Once biased to 1.5V,

the IC continuously monitors the voltage through external resistor

dividers, comparing each VMON pin voltage to an internal 0.633V

reference. At proper bias, OVSTATUS is pulled high, and

UVSTATUS and PGOOD are pulled low. Once the UVMON

input > VMON Vth continuously for ~160ms, its associated

STATUS output releases high, indicating that the minimum

voltage condition has been met. As both UVMON and OVMON

inputs are satisfied, the PGOOD output is released to go high,

indicating that the monitored voltage is within the specified

window. Figure 18 shows this performance for a 4V to 5V

window.

When VMON does not satisfy its voltage high or low criteria for

more than the glitch filter time, the associated STATUS and

PGOOD are pulled low. Figures 19 and 20 show this performance

for a 4V to 5V compliant window.

Figures 21 through 23 show the VMON glitch filter timing to

STATUS and PGOOD notification and transient immunity.

The ENABLE input, when pulled low, allows the monitoring and

reporting functions to be disabled. Figure 24 shows ENABLE high

to PGOOD timing for compliant voltage.

When choosing resistors for the divider, remember to keep the

current through the string bounded by power loss tolerance at the

top end and noise immunity at the bottom end. For most

applications, total divider resistance in the 10k -100krange

is advisable, with 1% tolerance resistors being used to reduce

monitoring error.

Figures 1 and 2 show that choosing the two resistor values is

straightforward for the ISL6131, because the ratio of resistance

should equal the ratio of the desired trip voltage to the internal

reference, 0.633V.

For the ISL6132, two dividers of two resistors each can be

employed to monitor the OV and UV levels for each voltage.

Otherwise, use a single three-resistor string for each voltage. In

the three-resistor divider string, the ratio of the desired

overvoltage trip point to the internal reference is equal to the

ratio of the two upper resistors to the lowest (GND connected)

resistor. The desired undervoltage trip point ratio to the internal

reference voltage is equal to the ratio of the uppermost (voltage

connected) resistor to the two lower resistors, as shown in the

following example:

1. Establish lower and upper trip level: 3.3V ±20% or 2.64V (UV)

and 3.96V (OV)

2. Establish total resistor string value: 10kIr = divider current

3. (Rm + Rl) * Ir = 0.623V @ UV and Rl * Ir = 0.633V @ OV

4. Rm + Rl = 0.623V/Ir @ UV => Rm + Rl =

0.623V/(2.64V/10kΩ) = 2.359kΩ

5. Rl = 0.633V/Ir @ OV => Rl = 0.633V/(3.96V/10kΩ) = 1.598kΩ

6. Rm = 2.359kΩ - 1.598kΩ = 0.761kΩ

7. Ru = 10kΩ - 2.397kΩ = 7.641kΩ

Choose standard value resistors that most closely approximate

these ideal values. Choosing a different total divider resistance

value may yield a more ideal ratio with available resistors values.

FN9119 Rev 6.00

February 11, 2014

Page 5 of 15

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