MCM6926AWJ10 Просмотр технического описания (PDF) - Motorola => Freescale

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Компоненты Описание

производитель

MCM6926AWJ10

128K x 8 Bit Fast Static Random Access Memory

Motorola => Freescale 

WRITE CYCLE 2 (E Controlled, See Notes 1 and 2)

6926A–8

6926A–10

6926A–12

6926A–15

Parameter

Symbol Min Max Min Max Min Max Min Max Unit Notes

Write Cycle Time

tAVAV

8

—

10

—

12

—

15

—

ns

3

Address Setup Time

Address Valid to End of Write

Enable to End of Write

tAVEL

0

—

0

—

0

—

0

—

ns

tAVEH

7

—

8

—

9

—

10

—

ns

tELEH,

7

—

8

—

9

—

10

—

ns

4,5

tELWH

Data Valid to End of Write

Data Hold Time

tDVEH

4

—

5

—

6

—

7

—

ns

tEHDX

0

—

0

—

0

—

0

—

ns

Write Recovery Time

tEHAX

0

—

0

—

0

—

0

—

ns

NOTES:

1. A write occurs during the overlap of E low and W low.

2. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycles.

3. All write cycle timings are referenced from the last valid address to the first transitioning address.

4. If E goes low coincident with or after W goes low, the output will remain in a high impedance condition.

5. If E goes high coincident with or before W goes high, the output will remain in a high impedance condition.

A (ADDRESS)

E (CHIP ENABLE)

W (WRITE ENABLE)

D (DATA IN)

WRITE CYCLE 2

tAVAV

tAVEH

tAVEL

tELEH

tELWH

tEHAX

tDVEH

DATA VALID

tEHDX

Q (DATA OUT)

HIGH–Z

MOTOROLA FAST SRAM

MCM6926A

7

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