DS2155 Просмотр технического описания (PDF) - Maxim Integrated
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DS2155 Datasheet PDF : 238 Pages
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DS2155
22.1 METHOD 1: HARDWARE SCHEME .........................................................................................................113
22.2 METHOD 2: INTERNAL REGISTER SCHEME BASED ON DOUBLE-FRAME ..............................................113
22.3 METHOD 3: INTERNAL REGISTER SCHEME BASED ON CRC4 MULTIFRAME ........................................116
23. HDLC CONTROLLERS ........................................................................................................................126
23.1 BASIC OPERATION DETAILS..................................................................................................................126
23.2 HDLC CONFIGURATION........................................................................................................................126
23.2.1 FIFO Control....................................................................................................................................130
23.3 HDLC MAPPING....................................................................................................................................131
23.3.1 Receive ..............................................................................................................................................131
23.3.2 Transmit ............................................................................................................................................133
23.3.3 FIFO Information .............................................................................................................................138
23.3.4 Receive Packet-Bytes Available........................................................................................................138
23.3.5 HDLC FIFOs ....................................................................................................................................139
23.4 RECEIVE HDLC CODE EXAMPLE..........................................................................................................140
23.5 LEGACY FDL SUPPORT (T1 MODE)......................................................................................................140
23.5.1 Overview ...........................................................................................................................................140
23.5.2 Receive Section .................................................................................................................................140
23.5.3 Transmit Section ...............................................................................................................................142
23.6 D4/SLC-96 OPERATION ........................................................................................................................142
24. LINE INTERFACE UNIT (LIU) ...........................................................................................................143
24.1 LIU OPERATION ....................................................................................................................................143
24.2 RECEIVER ..............................................................................................................................................143
24.2.1 Receive Level Indicator and Threshold Interrupt .............................................................................144
24.2.2 Receive G.703 Synchronization Signal (E1 Mode)...........................................................................144
24.2.3 Monitor Mode ...................................................................................................................................144
24.3 TRANSMITTER .......................................................................................................................................145
24.3.1 Transmit Short-Circuit Detector/Limiter ..........................................................................................145
24.3.2 Transmit Open-Circuit Detector.......................................................................................................145
24.3.3 Transmit BPV Error Insertion ..........................................................................................................145
24.3.4 Transmit G.703 Synchronization Signal (E1 Mode).........................................................................145
24.4 MCLK PRESCALER ...............................................................................................................................146
24.5 JITTER ATTENUATOR.............................................................................................................................146
24.6 CMI (CODE MARK INVERSION) OPTION...............................................................................................146
24.7 LIU CONTROL REGISTERS.....................................................................................................................147
24.8 RECOMMENDED CIRCUITS.....................................................................................................................156
24.9 COMPONENT SPECIFICATIONS...............................................................................................................158
25. PROGRAMMABLE IN-BAND LOOP CODE GENERATION AND DETECTION......................163
26. BERT FUNCTION ..................................................................................................................................170
26.1 STATUS ..................................................................................................................................................170
26.2 MAPPING ...............................................................................................................................................170
26.3 BERT REGISTER DESCRIPTIONS ...........................................................................................................172
26.4 BERT REPETITIVE PATTERN SET..........................................................................................................176
26.5 BERT BIT COUNTER .............................................................................................................................177
26.6 BERT ERROR COUNTER........................................................................................................................178
27. PAYLOAD ERROR-INSERTION FUNCTION (T1 MODE ONLY)................................................180
27.1 NUMBER-OF-ERRORS REGISTERS..........................................................................................................182
27.1.1 Number-of-Errors Left Register........................................................................................................183
28. INTERLEAVED PCM BUS OPERATION (IBO) ...............................................................................184
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