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DS2155 Просмотр технического описания (PDF) - Maxim Integrated

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Компоненты Описание
производитель
DS2155
MaximIC
Maxim Integrated MaximIC
DS2155 Datasheet PDF : 238 Pages
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DS2155
Signal Name:
RLOS/LOTC
Signal Description:
Receive Loss-of-Sync/Loss-of-Transmit Clock
Signal Type:
Output
A dual function output that is controlled by the CCR1.0 control bit. This pin can be programmed to either toggle
high when the synchronizer is searching for the frame and multiframe or to toggle high if the TCLK pin has not
been toggled for 5µs.
Signal Name:
RCL
Signal Description:
Receive Carrier Loss
Signal Type:
Output
Set high when the line interface detects a carrier loss.
Signal Name:
RSIGF
Signal Description:
Receive Signaling Freeze
Signal Type:
Output
Set high when the signaling data is frozen by either automatic or manual intervention. Used to alert downstream
equipment of the condition.
Signal Name:
BPCLK
Signal Description:
Backplane Clock
Signal Type:
Output
A user-selectable synthesized clock output that is referenced to the clock that is output at the RCLK pin.
Signal Name:
RPOSO
Signal Description:
Receive Positive-Data Output
Signal Type:
Output
Updated on the rising edge of RCLKO with bipolar data out of the line interface. This pin is normally connected to
RPOSI.
Signal Name:
RNEGO
Signal Description:
Receive Negative-Data Output
Signal Type:
Output
Updated on the rising edge of RCLKO with the bipolar data out of the line interface. This pin is normally
connected to RNEGI.
Signal Name:
RCLKO
Signal Description:
Receive Clock Output
Signal Type:
Output
Buffered recovered clock from the network. This pin is normally connected to RCLKI.
Signal Name:
RPOSI
Signal Description:
Receive Positive-Data Input
Signal Type:
Input
Sampled on the falling edge of RCLKI for data to be clocked through the receive-side framer. RPOSI and RNEGI
can be connected together for an NRZ interface. Can be internally connected to RPOSO by connecting the LIUC
pin high.
Signal Name:
RNEGI
Signal Description:
Receive Negative-Data Input
Signal Type:
Input
Sampled on the falling edge of RCLKI for data to be clocked through the receive-side framer. RPOSI and RNEGI
can be connected together for an NRZ interface. Can be internally connected to RNEGO by connecting the LIUC
pin high.
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