DS2155 Просмотр технического описания (PDF) - Maxim Integrated

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DS2155

T1/E1/J1 Single-Chip Transceiver

Maxim Integrated 

DS2155

Signal Name:

RCHBLK

Signal Description: Receive Channel Block

Signal Type:

Output

A user-programmable output that can be forced high or low during any of the 24 T1 or 32 E1 channels.

Synchronous with RCLK when the receive-side elastic store is disabled. Synchronous with RSYSCLK when the

receive-side elastic store is enabled. Useful for blocking clocks to a serial UART or LAPD controller in

applications where not all channels are used such as fractional service, 384kbps service, 768kbps, or ISDN–PRI.

Also useful for locating individual channels in drop-and-insert applications, for external per-channel loopback, and

for per-channel conditioning. See Section 18 for details.

Signal Name:

RSER

Signal Description: Receive Serial Data

Signal Type:

Output

Received NRZ serial data. Updated on rising edges of RCLK when the receive-side elastic store is disabled.

Updated on the rising edges of RSYSCLK when the receive-side elastic store is enabled.

Signal Name:

RSYNC

Signal Description: Receive Sync

Signal Type:

Input/Output

An extracted pulse, one RCLK wide, is output at this pin that identifies either frame (IOCR1.5 = 0) or multiframe

(IOCR1.5 = 1) boundaries. If set to output frame boundaries, then through IOCR1.6, RSYNC can also be set to

output double-wide pulses on signaling frames in T1 mode. If the receive-side elastic store is enabled, then this pin

can be enabled to be an input through IOCR1.4, at which a frame or multiframe boundary pulse is applied.

Signal Name:

RFSYNC

Signal Description: Receive Frame Sync

Signal Type:

Output

An extracted 8kHz pulse, one RCLK wide, is output at this pin that identifies frame boundaries.

Signal Name:

RMSYNC

Signal Description: Receive Multiframe Sync

Signal Type:

Output

An extracted pulse, one RCLK wide (elastic store disabled) or one RSYSCLK wide (elastic store enabled), is

output at this pin that identifies multiframe boundaries.

Signal Name:

RDATA

Signal Description: Receive Data

Signal Type:

Output

Updated on the rising edge of RCLK with the data out of the receive-side framer.

Signal Name:

RSYSCLK

Signal Description: Receive System Clock

Signal Type:

Input

1.544MHz, 2.048MHz, 4.096MHz, or 8.192MHz clock. Only used when the receive-side elastic store function is

enabled. Should be connected low in applications that do not use the receive-side elastic store. See Section 28 for

details on 4.096MHz and 8.192MHz operation using the IBO.

Signal Name:

RSIG

Signal Description:

Receive Signaling Output

Signal Type:

Output

Outputs signaling bits in a PCM format. Updated on rising edges of RCLK when the receive-side elastic store is

disabled. Updated on the rising edges of RSYSCLK when the receive-side elastic store is enabled.

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