M4A5-384/128-5SAC Просмотр технического описания (PDF) - Lattice Semiconductor

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M4A5-384/128-5SAC

ispMACH™ 4A CPLD Family High Performance E2CMOS® In-System Programmable Logic

Lattice Semiconductor 

Table 8. Register/Latch Operation

Configuration

Input(s)

CLK/LE 1

Q+

D-type Register

D=X

0,1, ↓ (↑)

Q

D=0

↑ (↓)

0

D=1

↑ (↓)

1

T-type Register

T=X

0, 1, ↓ (↑)

Q

T=0

↑ (↓)

Q

T=1

↑ (↓)

Q

D=X

1 (0)

Q

D-type Latch

D=0

0 (1)

0

D=1

0 (1)

1

Note:

1. Polarity of CLK/LE can be programmed

Although the macrocell shows only one input to the register, the XOR gate in the logic allocator allows the

D-, T-type register to emulate J-K, and S-R behavior. In this case, the available product terms are divided

between J and K (or S and R). When configured as J-K, S-R, or T-type, the extra product term must be used

on the XOR gate input for flip-flop emulation. In any register type, the polarity of the inputs can be

programmed.

The clock input to the flip-flop can select any of the four PAL block clocks in synchronous mode, with the

additional choice of either polarity of an individual product term clock in the asynchronous mode.

The initialization circuit depends on the mode. In synchronous mode (Figure 7), asynchronous reset and

preset are provided, each driven by a product term common to the entire PAL block.

Power-Up

Reset

PAL-Block

Initialization

Product Terms

AP AR

D/T/L Q

Power-Up

Preset

PAL-Block

Initialization

Product Terms

AP AR

D/L

Q

a. Power-up reset

b. Power-up preset

17466G-012

Figure 7. Synchronous Mode Initialization Configurations

17466G-013

12

ispMACH 4A Family

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