7585AILZ Просмотр технического описания (PDF) - Renesas Electronics
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7585AILZ Datasheet PDF : 19 Pages
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EL7585A
Electrical Specifications VDD = 5V, VBOOST = 11V, ILOAD = 200mA, VON = 15V, VOFF = -5V, VLOGIC = 2.5V, over temperature from
-40°C to 85°C, unless otherwise specified. (Continued)
PARAMETER
DESCRIPTION
CONDITION
MIN TYP MAX UNIT
OT
Over-temperature Threshold
140
°C
IPG
PG Pull-down Current
VPG>0.6V
VPG<0.6V
15
µA
1.7
mA
LOGIC ENABLE
VHI
VLO
ILOW
IHIGH
Logic High Threshold
Logic Low Threshold
Logic Low bias Current
Logic High bias Current
at VEN = 5V
2.2
V
0.8
V
0.2
1
µA
12
18
24
µA
Pin Descriptions
PIN NAME
PIN NUMBER
1
CDLY
2
3, 4
5
6
7
8
9, 17
10
11
12, 13
14
15
DELB
LX1, LX2
DRVP
FBP
DRVL
FBL
SGND
DRVN
FBN
PGND
VREF
CINT
16
FBB
18
EN
19
VDD
20
PG
DESCRIPTION
A capacitor connected from this pin to GND sets the delay time for start-up sequence and sets the fault
timeout time
Open drain output for gate drive of optional VBOOST delay FET
Drain of the internal N channel boost FET; for EL7586, pin 4 is not connected
Positive LDO base drive; open drain of an internal N channel FET
Positive LDO voltage feedback input pin; regulates to 1.2V nominal
Logic LDO base drive; open drain of an internal N channel FET
Logic LDO voltage feedback input pin; regulates to 1.2V nominal
Low noise signal ground
Negative LDO base drive; open drain of an internal P channel FET
Negative LDO voltage feedback input pin; regulates to 0.2V nominal
Power ground, connected to source of internal N channel boost FET
Bandgap voltage bypass, connect a 0.1µF to SGND
VBOOST integrator output, connect capacitor to SGND for PI mode or connect to VDD for P mode
operation
Boost regulator voltage feedback input pin; regulates to 1.2V nominal
Enable pin, High=Enable; Low or floating=Disable
Positive supply
Push-pull gate drive of optional fault protection FET, when chip is disabled or when a fault has been
detected, this is high
FN7523 Rev 3.00
March 9, 2006
Page 4 of 19
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