KM4470 Просмотр технического описания (PDF) - Fairchild Semiconductor
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KM4470 Datasheet PDF : 16 Pages
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DATA SHEET
Layout Considerations
General layout and supply bypassing play major roles in high
frequency performance. Fairchild has evaluation boards to
use as a guide for high frequency layout and as aid in device
testing and characterization. Follow the steps below as a
basis for high frequency layout:
• Include 6.8µF and 0.01µF ceramic capacitors
• Place the 6.8µF capacitor within 0.75 inches of
the power pin
• Place the 0.01µF capacitor within 0.1 inches of
the power pin
• Remove the ground plane under and around the
part, especially near the input and output pins to
reduce parasitic capacitance
• Minimize all trace lengths to reduce series
inductances
Refer to the evaluation board layouts shown in Figure 6 for
more information.
When evaluating only one channel, complete the
following on the unused channel:
1. Ground the non-inverting input
2. Short the output to the inverting input
Evaluation Board Information
The following evaluation boards are available to aid in the
testing and layout of this device:
Eval Bd
KEB002
KEB011
KEB006
KEB010
KEB012
Description
Single Channel, Dual Supply,
5 and 6 lead SOT23
Single Channel, Dual Supply,
5 and 6 lead SC70
Dual Channel, Dual Supply,
8 lead SOIC
Dual Channel, Dual Supply,
8 lead MSOP
Quad Channel, Dual Supply,
14 lead TSSOP
Products
KM4170IT5
KM4170IS5
KM4270IC8
KM4270IM8
KM4470IP14
Evaluation board schematics are shown in Figures 5a, 5b, 5c
and layouts are shown in Figure 6a through Figure 6l.
KM4170, KM4270, KM4470
Figure 5a: KM4170 Evaluation Board Schematic
Figure 5b: KM4270 Evaluation Board Schematic
8
REV. 5 December 2002
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