CY7C197N(2011) Просмотр технического описания (PDF) - Cypress Semiconductor

Номер в каталоге

Компоненты Описание

производитель

CY7C197N
(Rev.:2011)

256 K × 1 Static RAM

Cypress Semiconductor 

Switching Waveforms (continued)

Figure 6. Write Cycle No. 2 (CE Controlled)[13, 14]

ADDRESS

tSA

CE

WE

DATA IN

DATA OUT

tWC

tSCE

tAW

tHA

tPWE

tSD

tHD

DATA VALID

HIGH IMPEDANCE

CY7C197N

Notes

13. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can

terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.

14. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.

Document #: 001-06495 Rev. *D

Page 7 of 13

Share Link: