CY7C197B Просмотр технического описания (PDF) - Cypress Semiconductor
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CY7C197B Datasheet PDF : 10 Pages
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AC Electrical Characteristics5 6 7
Parameter
tRC
tAA
tOHA
tACE
tLZCE
tHZCE
tPU
tPD
tWC
tSCE
tAW
tHA
tSA
tPWE
tSD
tHD
tHZWE
tLZWE
Description
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE to Data Valid
CE to Low Z
CE to High Z
CE to Power-up
CE to Power-down
Write Cycle Time
CE to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
Data Set-up to Write End
Data Hold from Write End
WE LOW to High Z
WE HIGH to Low Z
12 ns
Min
Max
12
–
–
12
3
–
–
12
3
–
–
5
0
–
–
12
12
–
9
–
9
–
0
–
0
–
8
–
8
–
0
–
–
7
2
–
CY7C197B
25 ns
Min
Max
Unit
25
–
ns
–
25
ns
3
–
ns
–
25
ns
3
–
ns
–
11
ns
0
–
ns
–
20
ns
25
–
ns
20
–
ns
20
–
ns
0
–
ns
0
–
ns
20
–
ns
15
–
ns
0
–
ns
–
11
ns
3
–
ns
Notes:
5. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
6. tHZCE and tLZCE are specified with CL = 5 pF as in part (B) in AC Test Loads and Waveforms. Transition is measured +/-500 mV from steady-state
voltage.
7. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either
signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates
the write.
Document #: 38-05410 Rev. **
Page 6 of 10
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