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AN4506

L3GD20H: 3-axis digital output gyroscope

STMicroelectronics 

AN4506

Interrupt generation

5.2

Interrupt configuration

The L3GD20H offers several possibilities to personalize the interrupt signal. The registers

involved in the interrupt generation behavior are IG_CFG, IG_THS and IG_DURATION.

AND/OR

LIR

Table 18. IG_CFG register

ZHIE

ZLIE

YHIE

YLIE

XHIE

XLIE

AND/OR

LIR

ZHIE

ZLIE

YHIE

YLIE

XHIE

XLIE

Table 19. IG_CFG description

AND/OR combination of interrupt events. Default value: 0

(0: OR combination of interrupt events 1: AND combination of interrupt events

Latch interrupt request. Default value: 0

(0: interrupt request not latched; 1: interrupt request latched)

Cleared by reading IG_SRC reg.

Enable interrupt generation on Z high event. Default value: 0

(0: disable interrupt request; 1: enable interrupt request on measured rate value

higher than preset threshold)

Enable interrupt generation on Z low event. Default value: 0

(0: disable interrupt request; 1: enable interrupt request on measured rate value lower

than preset threshold)

Enable interrupt generation on Y high event. Default value: 0

(0: disable interrupt request; 1: enable interrupt request on measured rate value

higher than preset threshold)

Enable interrupt generation on Y low event. Default value: 0

(0: disable interrupt request; 1: enable interrupt request on measured rate value lower

than preset threshold)

Enable interrupt generation on X high event. Default value: 0

(0: disable interrupt request; 1: enable interrupt request on measured rate value

higher than preset threshold)

Enable interrupt generation on X low event. Default value: 0

(0: disable interrupt request; 1: enable interrupt request on measured rate value lower

than preset threshold)

AND/OR

0

1

Table 20. Interrupt mode configuration

Interrupt mode

OR combination of interrupt events

AND combination of interrupt events

Whenever an interrupt condition is verified the interrupt signal is generated and by reading

the IG_SRC register it is possible to understand which condition happened.

Reading IG_SRC also clears the IG_SRC IA bit (and eventually the interrupt signal on the

INT1 pin) and allows the refresh of data in the IG_SRC register if the latched option was

chosen.

DocID026442 Rev 2

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