LC74785M Просмотр технического описания (PDF) - SANYO -> Panasonic

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производитель

LC74785M

On-Screen Display Controller LSI

SANYO -> Panasonic 

LC74785, LC74785M

The timing of the transfer of caption data to the data output buffer is synchronized with the falling edge of the pulse

output from LN21. Therefore, the software processing shown below is required if the decoder LSI (microcontroller) does

not detect LN21 falling edges.

Activity within a given frame (MOD1: low)

Transfer of 16 data bits

Data in which all

16 bits are zero

Figure 5 Transferring caption data from the LC74785/M to the decoder LSI (microcontroller): Method 2

(When it is not possible to allocate a port on the decoder LSI (microcontroller) to detect

falling edges on LN21.)

Since data is output to the output buffer once (during the even field) when MOD1 is low, the data transfer control

operation from the decoder LSI (microcontroller) must be performed at least twice in a single frame (about 32 ms).

If a transfer control operation is performed twice in the same frame, the CPDT output on the second operation will be 16

bits of zero data. This allows the decoder LSI to determine that the data for the next frame has not been transferred yet.

Note: If CS2 remains low, the hardware will not be able to transfer the data to the output buffer. Therefore, the decoder LSI (microcontroller) must reset CS2

to high from low after it completes a data transfer control operation.

Transfer method 2 cannot be used if MOD1 is high (NTSC-TV).

No. 5520-8/24

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