LC74785M Просмотр технического описания (PDF) - SANYO -> Panasonic
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LC74785M Datasheet PDF : 24 Pages
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LC74785, LC74785M
Continued from preceding page.
Pin No.
15
16
17
18
Pin
CV IN
VDD1
SYNIN
CDLR
Function
Video signal input
Power supply
Sync separator circuit input
Background color phase adjustment
19
SEPOUT
Composite synchronizing signal output
20
SEP
IN
Vertical synchronizing signal input
21
CS2
Enable input
22
CPDT
Data output
23
RST
Reset input
24
VDD1
Power supply (+5 V)
Note: Both VDD1 pins must be connected to the power supply.
Notes
Composite video signal input
Power supply (+5 V: digital system power supply)
Video signal input for the built-in sync separator circuit
Background color phase adjustment. Connect to ground through a resistor and a capacitor.
Video signal output for the built-in sync separator circuit. Can be switched to function
as an output for signal (high or ST. pulse) due to MOD0 by setting SEL0 high.
Inputs the vertical synchronizing signal created by integrating the SEPOUT pin output
signal.
An integration circuit must be connected to the SEPOUT pin. This pin must be tied to
VDD1 if unused. This pin can be switched to function as the frame signal input mode
by setting SEL1 high. (This is valid when CTL3 is set to 1.)
EDS data output enable input. EDS data output is enabled when this pin is low. A
pull-up resistor is built in. (The input has hysteresis characteristics.)
EDS data output (This pin can be either an n-channel open-drain output or a CMOS
output.)
System reset input
A pull-up resistor is built in. (The input has hysteresis characteristics.)
Power supply (+5 V: digital system power supply)
Specifications
Absolute Maximum Ratings at Ta = 25°C
Parameter
Supply voltage
Input voltage
Output voltage
Allowable power dissipation
Operating temperature
Storage temperature
Symbol
VDD
VIN
VOUT
Pd max
Topr
Tstg
Conditions
VDD1 and VDD2
All input pins
LN21, CPDT, SEPOUT, and SYNCJDG
Ta = 25°C
Ratings
Unit
VSS–0.3 to VSS+7.0
V
VSS–0.3 to VDD+0.3
V
VSS–0.3 to VDD+0.3
V
350
mW
–30 to +70
°C
–40 to +125
°C
Allowable Operating Ranges at Ta = –30 to +70°C
Parameter
Symbol
Conditions
Ratings
min
typ
Supply voltage
Input high-level voltage
Input low-level voltage
Pull-up resistance
VDD1
VDD2
VIH1
VDD1
VDD2
RST, CS1, CS2, SIN, SCLK, SEPIN,
and MUTE
4.5
5.0
4.5
5.0
0.8VDD1
VIH2
VIL1
CTRL1
RST, CS1, CS2, SIN, SCLK, SEPIN,
and MUTE
0.7VDD1
VSS – 0.3
VIL2 CTRL1
VSS – 0.3
Applies to pins set for the RST, CS1, CS2,
RPU SIN, SCLK, and MUTE pin options.
25
50
Composite video signal input voltage
Input voltage
VIN1
VIN2
VIN3
FOSC1
CVIN; VDD1 = 5 V
SYNIN; VDD1 = 5 V
XtalIN (When external clock input is used)
fin = 2 fsc or 4 fsc ; VDD1 = 5 V
The XtalIN and XtalOUT oscillator pins
(2 fsc: NTSC)
2.0
1.5
2.0
0.10
7.159
Oscillator frequency
FOSC1
The XtalIN and XtalOUT oscillator pins
(4 fsc: NTSC)
14.318
FOSC2
The OSCIN and OSCOUT oscillator pins
(LC oscillator)
5
Note: When the XtalIN pin is used in clock input mode, extreme care must be taken to prevent noise from entering the input signal.
max
5.5
1.27VDD1
VDD1 + 0.3
VDD1 + 0.3
0.2VDD1
0.3VDD1
90
2.5
5.0
10
Unit
V
V
V
V
V
V
kΩ
Vp-p
Vp-p
Vp-p
MHz
MHz
MHz
No. 5520-3/24
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