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345R-XXLF
(Rev.:2013)

TRIPLE PLL FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER

Integrated Device Technology 

ICS345

TRIPLE PLL FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER

EPROM CLOCK SYNTHESIZER

Spread Spectrum Modulation

The ICS345 utilizes frequency modulation (FM) to distribute

energy over a range of frequencies. By modulating the

output clock frequencies, the device effectively lowers

energy across a broader range of frequencies; thus,

lowering a system’s electromagnetic interference (EMI). The

modulation rate is the time from transitioning from a

minimum frequency to a maximum frequency and then back

to the minimum.

Spread Spectrum Modulation can be applied as either

“center spread” or “down spread”. During center spread

modulation, the deviation from the target frequency is equal

in the positive and negative directions. The effective

average frequency is equal to the target frequency. In

applications where the clock is driving a component with a

maximum frequency rating, down spread should be applied.

In this case, the maximum frequency, including modulation,

is the target frequency. The effective average frequency is

less than the target frequency.

The ICS345 operates in both center spread and down

spread modes. For center spread, the frequency can be

modulated between ±0.125% to ±2.0%. For down spread,

the frequency can be modulated between -0.25% to -4.0%.

Both output frequency banks will utilize identical spread

spectrum percentage deviations and modulation rates, if a

common VCO frequency can be identified.

Spread Spectrum Modulation Rate

The spread spectrum modulation frequency applied to the

output clock frequency may occur at a variety of rates. For

applications requiring the driving of “down-circuit” PLLs,

Zero Delay Buffers, or those adhering to PCI standards, the

spread spectrum modulation rate should be set to 30-33

kHz. For other applications, a 120 kHz modulation option is

available.

Using VersaClock Products with an Input Clock

Source

In order to ensure proper startup with an input clock rather

than a crystal, the supply voltage must be within the

operating range (3.3V ±10%) and the input signal must be

stable and free from glitching. The input clock must provide

pulses of at least 20ns, and no more than 500ns, for at least

160 clock cycles without any interruptions to the clock or

power during this period. It may take up to 4ms for output

frequencies to reach their target frequency values.

An alternative method is to have the PDTS pin asserted low

while power supplies and clock sources stabilize.Once the

power supply and input clock source are constant and within

the acceptable frequency range, bring PDTS high. This

approach is preferred if the clock source is derived from

another PLL, or the source oscillator produces

unpredictable output pulses prior to stabilization. No

considerations need to be taken when using a crystal input

source with VersaClock products.

Absolute Maximum Ratings

Stresses above the ratings listed below can cause permanent damage to the ICS345. These ratings, which are

standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these

or any other conditions above those indicated in the operational sections of the specifications is not implied.

Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical

parameters are guaranteed only over the recommended operating temperature range.

Parameter

Supply Voltage, VDD

Inputs

Clock Outputs

Storage Temperature

Soldering Temperature

Junction Temperature

Condition

Referenced to GND

Referenced to GND

Referenced to GND

Max 10 seconds

Min.

-0.5

-0.5

-65

Typ.

Max.

7

VDD+0.5

VDD+0.5

150

260

125

Units

V

V

V

C

C

C

IDT® TRIPLE PLL FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER

4

ICS345

REV P 090613

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