AS8SLC128K32Q-12L/IT Просмотр технического описания (PDF) - Micross Components
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AS8SLC128K32Q-12L/IT Datasheet PDF : 10 Pages
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LOW POWER CHARACTERISTICS (L Version Only)
SRAM
AS8SLC128K32
VCC
CS\ 1-4
LOW VCC DATA RETENTION WAVEFORM
DATA RETENTION MODE
4.5V
tCDR
VDR > 2V
V
DR
4.5V
tR
NOTES
1. All voltages referenced to VSS (GND).
2. Worst case address switching.
3. ICC is dependent on output loading and cycle rates.
unloaded, and f=
1
t RC(MIN)
HZ.
The specified value applies with the outputs
4. This parameter guaranteed but not tested.
5. Test conditions as specified with output loading as
shown in Fig. 1 & 2 unless otherwise noted.
6. tHZCS, tHZOE and tHZWE are specified with CL= 5pF as in
Fig. 2. Transition is measured +/- 200 mV typical from
steady state voltage, allowing for actual tester RC time
constant.
7. At any given temperature and voltage condition,
tHZCS, is less than tLZCS, and tHZWE is less than tLZWE.
8. WE\ is HIGH for READ cycle.
9. Device is continuously selected. Chip selects and output
enable are held in their active state.
10. Address valid prior to or coincident with latest occur-
ring chip enable.
11. tRC= READ cycle time.
12. Chip enable (CS\) and write enable (WE\) can initiate
and terminate a WRITE cycle.
13. ICC is for full 32 bit mode.
AS8SLC128K32
Rev. 0.8 01/10
Micross Components reserves the right to change products or specifications without notice.
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