LC74761 Просмотр технического описания (PDF) - SANYO -> Panasonic
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LC74761 Datasheet PDF : 21 Pages
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LC74761, LC74761M
Second byte
DA0 to DA7 Register name
State
Register content
Function
0
7
c7
1
0
6
c6
1
0
5
c5
1
0
4
c4
1
Character code (from 00 to FF (hexadecimal))
0
3
c3
1
0
2
c2
1
0
1
c1
1
0
0
c0
1
Note: When the chip is reset by the RST pin, the register states (bits) are all cleared to 0.
3 COMMAND2: Vertical Display Position Setting Command
First byte
DA0 to DA7
7
6
5
4
3
2
1
0
Register name
—
—
—
—
SZ21
SZ20
SZ11
SZ10
State
1
0
1
0
0
1
0
1
0
1
0
1
Register content
Function
The command 2 identification code:
sets the vertical display position.
SZ20
SZ21
0
1
0
Normal size
Triple size
SZ10
SZ11
0
1
0
Normal size
Triple size
1
Double size
Normal size
1
Double size
Normal size
Second byte
DA0 to DA7 Register name
State
Register content
Function
7
—
0
Second byte identification code
6
—
0
VP5
0
The vertical display start position is given by
5
(MSB)
1
5
4
VP4
0
VS = H × ( Σ 2nVPn)
n=0
1
where H is the horizontal synchronization pulse period.
0
3
VP3
1
HSYNC
0
2
VP2
1
0
1
VP1
1
VP0
0
0
(LSB)
1
VSYNC
VS
HS
Character
display area
Note: When the chip is reset by the RST pin, the register states (bits) are all cleared to 0.
Note
Note
Character size for the second line
Character size for the first line
Note
The six bits VP0 to VP5 specify the
vertical display start position.
The weight of the lsb is 1 × H.
No. 4846-9/21
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