M25P16 Просмотр технического описания (PDF) - Micron Technology

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M25P16

Micron M25P16 Serial Flash Embedded Memory

Micron Technology 

Micron M25P16 Serial Flash Embedded Memory

SPI Modes

Figure 5: Bus Master and Memory Devices on the SPI Bus

R

SPI interface with

(CPOL, CPHA) =

(0, 0) or (1, 1)

SDO

SDI

SCK

SPI Bus Master

C

VCC

DQ1 DQ0

VSS

C

DQ1 DQ0

VCC

VSS

VSS

VCC

C

VCC

DQ1 DQ0

VSS

CS3

CS2 CS1

R

SPI memory

R

device

S#

W# HOLD#

SPI memory

R

device

S#

W# HOLD#

SPI memory

device

S#

W# HOLD#

Notes:

1. WRITE PROTECT (W#) and HOLD# should be driven HIGH or LOW as appropriate.

2. Resistors (R) ensure that the memory device is not selected if the bus master leaves the

S# line High-Z.

3. The bus master may enter a state where all I/O are High-Z at the same time; for exam-

ple, when the bus master is reset. Therefore, C must be connected to an external pull-

down resistor so that when all I/O are High-Z, S# is pulled HIGH while C is pulled LOW.

This ensures that S# and C do not go HIGH at the same time and that the tSHCH require-

ment is met.

4. The typical value of R is 100kΩ, assuming that the time constant R × Cp (Cp = parasitic

capacitance of the bus line) is shorter than the time during which the bus master leaves

the SPI bus High-Z.

5. Example: Given that Cp = 50pF (R × Cp = 5μs), the application must ensure that the bus

master never leaves the SPI bus High-Z for a time period shorter than 5μs.

PDF: 09005aef8456656c

m25p16.pdf - Rev. J 1/18 EN

11

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