KSZ8051MNL Просмотр технического описания (PDF) - Microchip Technology
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KSZ8051MNL Datasheet PDF : 66 Pages
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KSZ8051MNL/RNL
The strap-in pins are latched at the de-assertion of reset. In some systems, the MAC MII receive input pins may drive
high/low during power-up or reset, and consequently cause the PHY strap-in pins on the MII signals to be latched to
unintended high/low states. In this case, external pull-ups (4.7 kΩ) or pull-downs (1.0 kΩ) should be added on these
PHY strap-in pins to ensure that the intended values are strapped-in correctly.
TABLE 2-2: STRAP-IN OPTIONS - KSZ8051MNL
Pin Number Pin Name
Type
Note 2-4
Description
15
PHYAD2
Ipd/O PHYAD[2:0] is latched at de-assertion of reset and is configurable to
14
PHYAD1
Ipd/O any value from 0 to 7 with PHY Address 1 as the default value.
PHY Address 0 is assigned by default as the broadcast PHY
address, but it can be assigned as a unique PHY address after pull-
13
PHYAD0
Ipu/O ing the B-CAST_OFF strapping pin high or writing a ‘1’ to Register
16h, bit [9].
PHY Address bits [4:3] are set to 00 by default.
18
CONFIG2
The CONFIG[2:0] strap-in pins are latched at the de-assertion of
reset.
29
CONFIG1
Ipd/O
CONFIG[2:0] Mode
000
MII (default)
110
MII back-to-back
28
CONFIG0
001 – 101,
111
Reserved, not used
Isolate mode
Pull-up = Enable
20
ISO
Ipd/O Pull-down (default) = Disable
At the de-assertion of reset, this pin value is latched into Register 0h,
bit [10].
Speed mode
Pull-up (default) = 100 Mbps
31
SPEED
Ipu/O
Pull-down = 10 Mbps
At the de-assertion of reset, this pin value is latched into register 0h,
bit [13] as the speed select, and also is latched into register 4h (auto-
negotiation advertisement) as the speed capability support.
16
30
19
21
Note 2-4
DUPLEX
Ipu/O
Duplex Mode:
Pull-up (default) = Half-duplex
Pull-down = Full-duplex
At the de-assertion of reset, this pin value is latched into Register 0h,
Bit [8].
NWAYEN
Ipu/O
Nway Auto-Negotiation Enable:
Pull-up (default) = Enable auto-negotiation
Pull-down = Disable auto-negotiation
At the de-assertion of reset, this pin value is latched into Register 0h,
Bit [12].
B-CAST_OFF
Ipd/O
Broadcast Off – for PHY Address 0:
Pull-up = PHY Address 0 is set as an unique PHY address
Pull-down (default) = PHY Address 0 is set as a broadcast PHY
address
At the de-assertion of reset, this pin value is latched by the chip.
NAND Tree Mode:
NAND_Tree#
Ipu/Opu
Pull-up (default) = Disable
Pull-down = Enable
At the de-assertion of reset, this pin value is latched by the chip.
Ipu/O = Input with internal pull-up during power-up/reset; output pin otherwise.
Ipd/O = Input with internal pull-down during power-up/reset; output pin otherwise.
Ipu/Opu = Input with internal pull-up and output with internal pull-up.
2016 Microchip Technology Inc.
DS00002310A-page 9
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