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EN5336QI

3A PowerSoC Voltage Mode Synchronous Buck With Integrated Inductor Output Voltage Programming

Altera Corporation 

EN5336QI

Table 2. Recommended input capacitors.

Description

10uF, 10V, 10%

X7R, 1206

(2 capacitors needed)

22uF, 10V, 10%

X5R, 1210

(1 capacitor needed)

MFG

Murata

Taiyo Yuden

Murata

Taiyo Yuden

P/N

GRM31CR71A106KA01L

LMK316B7106KL-T

GRM32ER71A226KE20L

LM K325B7226KM -T

Output Capacitor Selection

The EN5336QI has been optimized for use with

approximately 50μF of output capacitance. Low

ESR ceramic capacitors are required with X5R or

X7R rated dielectric formulation. Y5V or

equivalent dielectric formulations must not be

used as these lose capacitance with frequency,

temperature and bias voltage.

Output ripple voltage is determined by the

aggregate output capacitor impedance. Output

impedance, denoted as Z, is comprised of

effective series resistance, ESR, and effective

series inductance, ESL:

Z = ESR + ESL.

Placing output capacitors in parallel reduces the

impedance and will hence result in lower ripple

voltage.

1  1  1  ...  1

ZTotal Z1 Z 2

Zn

Enable Operation

The ENABLE pin provides a means to shut down

the device, or enable normal operation. A logic

high will enable the converter into normal

operation. When the ENABLE pin is asserted,

the device will undergo a normal soft start. A

logic low will disable the converter and cause it to

shut down. When Enable goes low, circuitry

internal to the device continue to operate to

ensure the output voltage is gradually returned to

zero and the circuits turn off subsequently. A

short low going pulse on Enable is ignored.

Soft-Start Operation

Soft start is a method to reduce in-rush current

when the device is enabled. The output voltage

is ramped up slowly upon start-up. The output

rise time is controlled by choice of a soft-start

capacitor, which is placed between the SS pin

(pin 37) and the AGND pin (pin 29).

Rise Time: TR = Css* 75K

During start-up of the converter, the reference

voltage to the error amplifier is gradually

increased from zero to its final level by an

internal current source of typically 10uA. Typical

soft-start rise time is 1mS to 3mS. The rise time

is measured from the time when AVIN > VUVLO

and the Enable signal crosses its logic high

threshold. Typical SS capacitor values are in the

range of 15nF to 50 nF.

Typical ripple versus capacitance is given below:

Output Capacitor

Configuration

1 x 47 uF

3 x 22 uF

Typical Output Ripple (mVp-p)

(as measured on EN5336QI

Evaluation Board)

30

15

Power-up Sequencing

The sequencing of AVIN, PVIN and ENABLE

should meet the following requirements:

1. ENABLE should not be asserted before PVIN.

2. PVIN should not be applied before AVIN.

Table 3. Recommended output capacitors.

Description

22uF, 6.3V, 10%

X5R, 1206

(3 capacitors needed)

47uF, 10V, 10%

X5R, 1210

47uF, 6.3V, 10%

X5R, 1210

(1 capacitor needed)

MFG

Murata

P/N

GRM31CR60J226KE19L

Taiyo Yuden

JMK316BJ226KL-T

Murata

GRM32ER61A476KE20L

AVX

12106D476KAT 2

Note that tying AVIN, PVIN and ENABLE

together and brought up at the same time does

meet these requirements.

POK Operation

The POK signal is an open drain signal from the

converter indicating the output voltage is within

the specified range. The POK signal will be a

logic high when the output voltage is above 90%

9

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