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EN5336QI

3A PowerSoC Voltage Mode Synchronous Buck With Integrated Inductor Output Voltage Programming

Altera Corporation 

EN5336QI

of VOUT and below the user programmed OVP

trip-point. If the output voltage goes outside of

this range, the POK signal will be a logic low until

the output voltage has returned to within this

range. In the event of an over-voltage condition

the POK signal will go low and will remain in this

condition until the output voltage has dropped to

95% of the programmed output voltage before

returning to the high state.

NOTE: If no over voltage protection is used, POK

will remain “high” as long as VOUT remains above

90% of the nominal VOUT setting.

stops, the lower N-MOSFET is turned on and the

POK signal goes low. When the output voltage

drops below 95% of the programmed output

voltage, normal PWM operation resumes and

POK returns to its high state.

Thermal Overload Protection

Thermal shutdown will disable operation once

the Junction temperature exceeds approximately

150ºC. Once the junction temperature drops by

approx 25ºC, the converter will re-start with a

normal soft-start.

Over-Current Protection

The current limit function is achieved by sensing

the current flowing through the sense P-

MOSFET. When the sensed current exceeds the

current limit, both NFET and PFET switches are

turned off. If the over-current condition is

removed, the over-current protection circuit will

enable the PWM operation. This circuit is

designed to provide high noise immunity.

The nominal over current trip point is set to 4.5A.

It is possible to increase the over-current set

point by about 50% by connecting a 7.5k

resistor between ROCP (pin 27) and GND. The

typical voltage at the ROCP pin is 0.75V.

In some cases, such as the start-up of FPGA

devices, it is desirable to blank the over-current

protection feature. In order to disable over-

current protection, the ROCP pin should be tied

to any voltage between 2.5V and PVIN.

Over-Voltage Protection

When the output voltage exceeds 120% of the

programmed output voltage, the PWM operation

Input Under-voltage Lock-out

Circuitry is provided to ensure that when the

input voltage is below the specified voltage

range, the converter will not start-up. Circuits for

hysteresis, input de-glitch and output leading

edge blanking are included to ensure high noise

immunity and prevent false tripping.

Compensation

The EN5336QI is internally compensated

through the use of a type 3 compensation

network and is optimized for use with about 50uF

of output capacitance and will provide excellent

loop bandwidth and transient performance for

most applications. (See the section on Capacitor

Selection for details on recommended capacitor

types.) Voltage mode operation provides high

noise immunity at light load.

In some cases modifications to the compensation

may be required. For more information, contact

Power Applications support.

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