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EN5335QI

3A PowerSoC Voltage Mode Synchronous Buck PWM DC-DC Converter with Integrated Inductor 3-Pin Programmable Output

Altera Corporation 

EN5335QI

Placing output capacitors in parallel reduces the

impedance and will hence result in lower ripple

voltage.

1 11

1

   ... 

ZTotal Z1 Z 2

Zn

increased from zero to its final level by an

internal current source of typically 10uA. Typical

soft-start rise time is 1mS to 3mS. The rise time

is measured from the time when AVIN > VUVLO

and the Enable signal crosses its logic high

threshold. Typical SS capacitor values are in the

range of 15nF to 50 nF.

Typical ripple versus capacitance is given below: Power-Up/Down Sequencing

Output Capacitor

Configuration

1 x 47 uF

3 x 22 uF

Typical Output Ripple (mVp-p)

(as measured on EN5335QI

Evaluation Board)

30

15

Table 3. Recommended output capacitors.

Description

22uF, 6.3V, 10%

X5R, 1206

(3 capacitors needed)

47uF, 10V, 10%

X5R, 1210

47uF, 6.3V, 10%

X5R, 1210

(1 capacitor needed)

MFG

Murata

P/N

GRM31CR60J226KE19L

Taiyo Yuden

JMK316BJ226KL-T

Murata

GRM32ER61A476KE20L

AVX

12106D476KAT 2 A

Enable Operation

The ENABLE pin provides a means to shut down

the device, or enable normal operation. A logic

high will enable the converter into normal

operation. When the ENABLE pin is asserted,

the device will undergo a normal soft start. A

logic low will disable the converter and cause it to

shut down. When Enable goes low, circuitry

internal to the device continue to operate to

ensure the output voltage is gradually returned to

zero and the circuits turn off subsequently. A

short low going pulse on Enable is ignored.

Soft-Start Operation

Soft start is a method to reduce in-rush current

when the device is enabled. The output voltage

is ramped up slowly upon start-up. The output

rise time is controlled by choice of a soft-start

capacitor, which is placed between the SS pin

(pin 37) and the AGND pin (pin 29).

During power-up, ENABLE should not be

asserted before PVIN, and PVIN should not be

asserted before AVIN. The PVIN should never

be powered when AVIN is off. During power

down, the AVIN should not be powered down

before the PVIN. Tying PVIN and AVIN or all

three pins (AVIN, PVIN, ENABLE) together

during power up or power down meets these

requirements.

Pre-Bias Start-up

The EN5335QI does not support startup into a

pre-biased condition. Be sure the output

capacitors are not charged or the output of the

EN5335QI is not pre-biased when the EN5335QI

is first enabled.

POK Operation

The POK signal is an open drain signal from the

converter indicating the output voltage is within

the specified range. The POK signal will be a

logic high when the output voltage is within 90% -

120% of the programmed output voltage. If the

output voltage goes outside of this range, the

POK signal will be a logic low until the output

voltage has returned to within this range. In the

event of an over-voltage condition the POK

signal will go low and will remain in this condition

until the output voltage has dropped to 95% of

the programmed output voltage before returning

to the high state (see also: Over-Voltage

Protection).

Rise Time: TR = Css* 75K

During start-up of the converter, the reference

voltage to the error amplifier is gradually

00846

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October 11, 2013

www.altera.com/enpirion

Rev J

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