ML6692CH Просмотр технического описания (PDF) - Micro Linear Corporation
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ML6692CH Datasheet PDF : 21 Pages
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ML6692
AC ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
MDC-MDIO (MII MANAGEMENT INTERFACE)
tSPWS
Write Setup Time, MDIO Data
Valid to MDC Rising Edge
1.4V Point
tSPWH
Write Hold Time, MDIO Data
Valid After MDC Rising Edge
1.4V Point
tSPRS
Read Setup Time, MDIO Data
Valid to MDC Rising Edge
1.4V Point
tSPRH
Read Hold time, MDIO Data
Valid After MDC Rising Edge
1.4V Point
tCPER Period of MDC
tCPW Pulsewidth of MDC
INITIALIZATION INTERFACE
tPW1
tPW2
tPER1
tDV1
ECLK Positive Pulsewidth
ECLK Negative Pulsewidth
ECLK Period, EEPROM Mode
EDOUT Data Valid Time After
ECLK Rising Edge
tPER2
tPW3
tPW4
tS1
tH1
ECLK period
ECLK Positive Pulsewidth
ECLK Negative Pulsewidth
ECLK Data Setup Time
ECLK Data Hold Time
CONDITIONS
MIN
TYP
MAX UNITS
10
ns
10
ns
100
ns
0
ns
400
Positive or negative pulses
160
EDIN floating (EEPROM Mode)
EDIN floating (EEPROM Mode)
EDIN floating (EEPROM Mode)
EDIN floating (EEPROM Mode)
900
900
1800
EDIN high (Microcontroller Mode)
EDIN high (Microcontroller Mode)
EDIN high (Microcontroller Mode)
EDIN high (Microcontroller Mode)
EDIN high (Microcontroller Mode)
5000
2000
2000
10
10
ns
ns
ns
ns
ns
900
ns
ns
ns
ns
ns
ns
Note 1. Limits are guaranteed by 100% testing, sampling, or correlation with worst case test conditions.
Note 2. Measured using the test circuit shown in fig. 1, under the following conditions:
RLP = 200W, RLS = 49.9W, RTSET = 2.49kW.
All resistors are 1% tolerance.
Note 3. Output current amplitude is IOUT = 40W 1.25V/RTSET.
Note 4. Measured relative to ideal negative and positive signal 50% points, using the four successive MLT-3 transitions for the 01010101 bit sequence.
Note 5. Time difference between 10% and 90% levels of the transition from the baseline voltage (nominally zero) to either the positive or negative peak signal
voltage. The times specified here correlate to the transition times defined in the ANSI X3T9.5 TP-PMD Rev 2.0 working draft, section 9.1.6, which include the
effects of the external network coupling transformer and EMI/RFI emissions filter.
Note 6. Differential test load is shown in fig. 1 (see note 2).
Note 7. Defined as the percentage excursion of the differential signal transition beyond its final adjusted value during the symbol interval following the transition. The
adjusted value is obtained by doing a straight line best-fit to an output waveform containing 14 bit-times of no transition preceded by a transition from zero to
either a positive or negative signal peak; the adjusted value is the point at which the straight line fit meets the rising or falling signal edge.
Note 8. From first rising edge of TXCLK after TXEN goes high, to first bit of J at the MDI.
Note 9. From first bit of J at the MDI, to CRS.
Note 10. From first bit of J at the MDI, to first rising edge of RXCLK after RXDV goes high.
10
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