SPT7710BIG Просмотр технического описания (PDF) - Cadeka Microcircuits LLC.

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SPT7710BIG

8-BIT, 150 MSPS, FLASH A/D CONVERTER

Cadeka Microcircuits LLC. 

Figure 1 – Typical Interface Circuit 1

*See below

Analog Input

Can Be Either

+

Voltage

Force Or Sense

U1

Limiter

RT

–

VRTF

Typical Voltage Limiter

RS

49.9

D1

D2

–5.2

D1=D2=HP, 1N 5712

VR2

.01 µF

VEE

VRef

–2 V

+

2.2

–U2.01 µF

10

Q1 (1N2907A)

VRBF

Analog Input

Can Be Either

VEE

Force Or Sense

VIN

Convert 100116

CLK

CLK

–2 V

(Analog)

.01 µF

L

VIN

AGND

VEE

2.2 µF –5.2 V

.01 µF

Preamp Comparator

256

Clock

Buffer

255

152

151

128

256 To

8-Bit

Encoder

127

64

63

2

1

2

AGND

.01 µF

VEE

–5.2 V

LINV

MINV

MSB D7

D6

D5

D4

ECL

Latches

And

Buffers

D3

D2

D1

LSB D0

50 W

DGND

.01 µF

–2 V (Digital)

50 W

GENERAL DESCRIPTION

The SPT7710 is a fast monolithic 8-bit parallel flash A/D

converter. The nominal conversion rate is 150 MSPS and

the analog bandwidth is in excess of 200 MHz. A major

advance over previous flash converters is the inclusion of

256 input preamplifiers between the reference ladder and

input comparators. (See block diagram.) This not only re-

duces clock transient kickback to the input and reference

ladder due to a low AC beta but also reduces the effect of

the dynamic state of the input signal on the latching char-

acteristics of the input comparators. The preamplifiers act

as buffers and stabilize the input capacitance so that it re-

mains constant for varying input voltages and frequencies

and, therefore, makes the part easier to drive than previ-

ous flash converters. The SPT7710 incorporates a propri-

etary decoding scheme that reduces metastable errors

(sparkle codes or flyers) to a maximum of 1 LSB.

The SPT7710 has true differential analog and digital data

paths from the preamplifiers to the output buffers (Current

Mode Logic) for reducing potential missing codes while

rejecting common mode noise.

Signature errors are also reduced by careful layout of the

analog circuitry. Every comparator also has a clock buffer

to reduce differential delays and to improve signal-to-

noise ratio. The output drive capability of the device can

provide full ECL swings into 50 Ω loads.

TYPICAL INTERFACE CIRCUIT

The typical interface circuit is shown in figure 1. The

SPT7710 is relatively easy to apply depending on the

accuracy needed in the intended application. Wire-wrap

may be employed with careful point-to-point ground con-

nections if desired, but to achieve the best operation, a

SPT7710

5

8/17/01

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