UC2844B Просмотр технического описания (PDF) - Motorola => Freescale

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UC2844B

High Performance Current Mode Controllers

Motorola => Freescale 

UC3844B, 45B UC2844B, 45B

Undervoltage Lockout

Two undervoltage lockout comparators have been

incorporated to guarantee that the IC is fully functional before

the output stage is enabled. The positive power supply

terminal (VCC) and the reference output (Vref) are each

monitored by separate comparators. Each has built–in

hysteresis to prevent erratic output behavior as their

respective thresholds are crossed. The VCC comparator

upper and lower thresholds are 16 V/10 V for the UCX844B,

and 8.4 V/7.6 V for the UCX845B. The Vref comparator upper

and lower thresholds are 3.6 V/3.4 V. The large hysteresis

and low startup current of the UCX844B makes it ideally

suited in off–line converter applications where efficient

bootstrap startup techniques are required (Figure 29). The

UCX845B is intended for lower voltage dc–to–dc converter

applications. A 36 V zener is connected as a shunt regulator

from VCC to ground. Its purpose is to protect the IC from

excessive voltage that can occur during system startup. The

minimum operating voltage for the UCX844B is 11 V and 8.2

V for the UCX845B.

Output

These devices contain a single totem pole output stage

that was specifically designed for direct drive of power

MOSFETs. It is capable of up to ±1.0 A peak drive current and

has a typical rise and fall time of 50 ns with a 1.0 nF load.

Additional internal circuitry has been added to keep the

Output in a sinking mode whenever an undervoltage lockout

is active. This characteristic eliminates the need for an

external pull–down resistor.

The SO–14 surface mount package provides separate

pins for VC (output supply) and Power Ground. Proper

implementation will significantly reduce the level of switching

transient noise imposed on the control circuitry. This

becomes particularly useful when reducing the Ipk(max) clamp

level. The separate VC supply input allows the designer

added flexibility in tailoring the drive voltage independent of

VCC. A zener clamp is typically connected to this input when

driving power MOSFETs in systems where VCC is greater

than 20 V. Figure 22 shows proper power and control ground

connections in a current–sensing power MOSFET

application.

Reference

The 5.0 V bandgap reference is trimmed to ±1.0%

tolerance at TJ = 25°C on the UC284XB, and ±2.0% on the

UC384XB. Its primary purpose is to supply charging current

to the oscillator timing capacitor. The reference has

short–circuit protection and is capable of providing in excess

of 20 mA for powering additional control system circuitry.

Design Considerations

Do not attempt to construct the converter on

wire–wrap or plug–in prototype boards. High frequency

circuit layout techniques are imperative to prevent

pulse–width jitter. This is usually caused by excessive noise

pick–up imposed on the Current Sense or Voltage Feedback

inputs. Noise immunity can be improved by lowering circuit

impedances at these points. The printed circuit layout should

contain a ground plane with low–current signal and

high–current switch and output grounds returning on

separate paths back to the input filter capacitor. Ceramic

bypass capacitors (0.1 µF) connected directly to VCC, VC,

and Vref may be required depending upon circuit layout. This

provides a low impedance path for filtering the high frequency

noise. All high current loops should be kept as short as

possible using heavy copper runs to minimize radiated EMI.

The Error Amp compensation circuitry and the converter

output voltage divider should be located close to the IC and

as far as possible from the power switch and other

noise–generating components.

Figure 17. External Clock Synchronization

Vref

8(14)

RT

R

Bias

R

CT 4(7)

0.01

External

Sync

Input

47 2(3)

1(1)

+

EA

Osc

2R

R

5(9)

The diode clamp is required if the Sync amplitude is large enough to cause

the bottom side of CT to go more than 300 mV below ground.

Figure 18. External Duty Cycle Clamp and

Multi–Unit Synchronization

8(14)

RA

8

RB

6

5.0k

4

3

R

4(7)

5

5.0k

Q

2

S

7

C

5.0k

MC1455

2(3)

1

1(1)

R

Bias

R

Osc

+

2R

EA

R

To Additional

5(9)

UCX84XBs

+ ) + ) f

1.44

(RA 2RB)C

D(max)

RA

RA 2RB

MOTOROLA ANALOG IC DEVICE DATA

9

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